17  * - In .apply() PWM output need to write register FREQ and DUTY. When first write FREQ
18  *     done and not yet write DUTY, it has short timing gap use new FREQ and old DUTY.
59 	u32 dd_freq, duty, mode0, mode1;  in sunplus_pwm_apply()  local
102 	/* cal and set pwm duty */  in sunplus_pwm_apply()
110 		duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | SP7021_PWM_DUTY_MAX;  in sunplus_pwm_apply()
116 		duty = mul_u64_u64_div_u64(state->duty_cycle, clk_rate,  in sunplus_pwm_apply()
118 		duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | duty;  in sunplus_pwm_apply()
120 	writel(duty, priv->base + SP7021_PWM_DUTY(pwm->hwpwm));  in sunplus_pwm_apply()
131 	u32 mode0, dd_freq, duty;  in sunplus_pwm_get_state()  local
139 		duty = readl(priv->base + SP7021_PWM_DUTY(pwm->hwpwm));  in sunplus_pwm_get_state()
140 		duty = FIELD_GET(SP7021_PWM_DUTY_MASK, duty);  in sunplus_pwm_get_state()
148 		 * dd_freq 16 bits, duty 8 bits, NSEC_PER_SEC 30 bits, won't overflow.  in sunplus_pwm_get_state()
150 		state->duty_cycle = DIV64_U64_ROUND_UP((u64)dd_freq * (u64)duty * NSEC_PER_SEC,  in sunplus_pwm_get_state()