Lines Matching +full:duty +full:- +full:cycle
1 // SPDX-License-Identifier: GPL-2.0
60 return readl_relaxed(spc->base + offset); in sprd_pwm_read()
68 writel_relaxed(val, spc->base + offset); in sprd_pwm_write()
75 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_get_state()
76 u32 val, duty, prescale; in sprd_pwm_get_state() local
84 ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM, chn->clks); in sprd_pwm_get_state()
87 pwm->hwpwm); in sprd_pwm_get_state()
91 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE); in sprd_pwm_get_state()
93 state->enabled = true; in sprd_pwm_get_state()
95 state->enabled = false; in sprd_pwm_get_state()
100 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. in sprd_pwm_get_state()
103 * duty_ns = NSEC_PER_SEC * (prescale + 1) * duty / clk_rate in sprd_pwm_get_state()
105 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE); in sprd_pwm_get_state()
108 state->period = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate); in sprd_pwm_get_state()
110 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY); in sprd_pwm_get_state()
111 duty = val & SPRD_PWM_DUTY_MSK; in sprd_pwm_get_state()
112 tmp = (prescale + 1) * NSEC_PER_SEC * duty; in sprd_pwm_get_state()
113 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate); in sprd_pwm_get_state()
114 state->polarity = PWM_POLARITY_NORMAL; in sprd_pwm_get_state()
117 if (!state->enabled) in sprd_pwm_get_state()
118 clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks); in sprd_pwm_get_state()
126 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_config()
127 u32 prescale, duty; in sprd_pwm_config() local
133 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. in sprd_pwm_config()
140 duty = duty_ns * SPRD_PWM_MOD_MAX / period_ns; in sprd_pwm_config()
142 tmp = (u64)chn->clk_rate * period_ns; in sprd_pwm_config()
144 prescale = DIV_ROUND_CLOSEST_ULL(tmp, SPRD_PWM_MOD_MAX) - 1; in sprd_pwm_config()
149 * Note: Writing DUTY triggers the hardware to actually apply the in sprd_pwm_config()
150 * values written to MOD and DUTY to the output, so must keep writing in sprd_pwm_config()
151 * DUTY last. in sprd_pwm_config()
156 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale); in sprd_pwm_config()
157 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX); in sprd_pwm_config()
158 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty); in sprd_pwm_config()
167 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_apply()
168 struct pwm_state *cstate = &pwm->state; in sprd_pwm_apply()
171 if (state->polarity != PWM_POLARITY_NORMAL) in sprd_pwm_apply()
172 return -EINVAL; in sprd_pwm_apply()
174 if (state->enabled) { in sprd_pwm_apply()
175 if (!cstate->enabled) { in sprd_pwm_apply()
181 chn->clks); in sprd_pwm_apply()
185 pwm->hwpwm); in sprd_pwm_apply()
190 ret = sprd_pwm_config(spc, pwm, state->duty_cycle, in sprd_pwm_apply()
191 state->period); in sprd_pwm_apply()
195 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 1); in sprd_pwm_apply()
196 } else if (cstate->enabled) { in sprd_pwm_apply()
202 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 0); in sprd_pwm_apply()
204 clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks); in sprd_pwm_apply()
231 if (ret == -ENOENT) in sprd_pwm_clk_init()
243 return dev_err_probe(dev, -ENODEV, "no available PWM channels\n"); in sprd_pwm_clk_init()
255 npwm = sprd_pwm_clk_init(&pdev->dev, chn); in sprd_pwm_probe()
259 chip = devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*spc)); in sprd_pwm_probe()
264 spc->base = devm_platform_ioremap_resource(pdev, 0); in sprd_pwm_probe()
265 if (IS_ERR(spc->base)) in sprd_pwm_probe()
266 return PTR_ERR(spc->base); in sprd_pwm_probe()
268 memcpy(spc->chn, chn, sizeof(chn)); in sprd_pwm_probe()
270 chip->ops = &sprd_pwm_ops; in sprd_pwm_probe()
272 ret = devm_pwmchip_add(&pdev->dev, chip); in sprd_pwm_probe()
274 dev_err(&pdev->dev, "failed to add PWM chip\n"); in sprd_pwm_probe()
280 { .compatible = "sprd,ums512-pwm", },
287 .name = "sprd-pwm",