40 	unsigned long duty;  member
84 	tmp = readl_relaxed(pc->base + pc->data->regs.duty);  in rockchip_pwm_get_state()
106 	unsigned long period, duty;  in rockchip_pwm_config()  local
113 	 * Since period and duty cycle registers have a width of 32  in rockchip_pwm_config()
122 	duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);  in rockchip_pwm_config()
125 	 * Lock the period and duty of previous configuration, then  in rockchip_pwm_config()
126 	 * change the duty and period, that would not be effective.  in rockchip_pwm_config()
135 	writel(duty, pc->base + pc->data->regs.duty);  in rockchip_pwm_config()
147 	 * the configuration of duty, period and polarity  in rockchip_pwm_config()
234 		.duty = 0x04,
247 		.duty = 0x08,
261 		.duty = 0x08,
275 		.duty = 0x08,