1 // SPDX-License-Identifier: GPL-2.0-only
3  * Intel Low Power Subsystem PWM controller driver
24 #include "pwm-lpss.h"
26 #define PWM				0x00000000  macro
32 /* Size of each PWM register space if multiple */
74 static inline u32 pwm_lpss_read(const struct pwm_device *pwm)  in pwm_lpss_read()  argument
76 	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);  in pwm_lpss_read()
78 	return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);  in pwm_lpss_read()
81 static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)  in pwm_lpss_write()  argument
83 	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);  in pwm_lpss_write()
85 	writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);  in pwm_lpss_write()
88 static int pwm_lpss_wait_for_update(struct pwm_device *pwm)  in pwm_lpss_wait_for_update()  argument
90 	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);  in pwm_lpss_wait_for_update()
91 	const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;  in pwm_lpss_wait_for_update()
97 	 * PWM Configuration register has SW_UPDATE bit that is set when a new  in pwm_lpss_wait_for_update()
102 	 * the bit enabled, PWM may freeze. That is, while one can still write  in pwm_lpss_wait_for_update()
109 		dev_err(pwmchip_parent(pwm->chip), "PWM_SW_UPDATE was not cleared\n");  in pwm_lpss_wait_for_update()
114 static inline int pwm_lpss_is_updating(struct pwm_device *pwm)  in pwm_lpss_is_updating()  argument
116 	if (pwm_lpss_read(pwm) & PWM_SW_UPDATE) {  in pwm_lpss_is_updating()
117 		dev_err(pwmchip_parent(pwm->chip), "PWM_SW_UPDATE is still set, skipping update\n");  in pwm_lpss_is_updating()
118 		return -EBUSY;  in pwm_lpss_is_updating()
124 static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,  in pwm_lpss_prepare()  argument
128 	unsigned long c = lpwm->info->clk_rate, base_unit_range;  in pwm_lpss_prepare()
138 	base_unit_range = BIT(lpwm->info->base_unit_bits);  in pwm_lpss_prepare()
143 	base_unit = clamp_val(base_unit, 1, base_unit_range - 1);  in pwm_lpss_prepare()
147 	on_time_div = 255ULL - on_time_div;  in pwm_lpss_prepare()
149 	ctrl = pwm_lpss_read(pwm);  in pwm_lpss_prepare()
151 	ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);  in pwm_lpss_prepare()
155 	pwm_lpss_write(pwm, ctrl);  in pwm_lpss_prepare()
156 	pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE);  in pwm_lpss_prepare()
159 static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)  in pwm_lpss_cond_enable()  argument
162 		pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);  in pwm_lpss_cond_enable()
166 				   struct pwm_device *pwm,  in pwm_lpss_prepare_enable()  argument
171 	ret = pwm_lpss_is_updating(pwm);  in pwm_lpss_prepare_enable()
175 	pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);  in pwm_lpss_prepare_enable()
176 	pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);  in pwm_lpss_prepare_enable()
177 	ret = pwm_lpss_wait_for_update(pwm);  in pwm_lpss_prepare_enable()
181 	pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);  in pwm_lpss_prepare_enable()
185 static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,  in pwm_lpss_apply()  argument
191 	if (state->enabled) {  in pwm_lpss_apply()
192 		if (!pwm_is_enabled(pwm)) {  in pwm_lpss_apply()
194 			ret = pwm_lpss_prepare_enable(lpwm, pwm, state);  in pwm_lpss_apply()
198 			ret = pwm_lpss_prepare_enable(lpwm, pwm, state);  in pwm_lpss_apply()
200 	} else if (pwm_is_enabled(pwm)) {  in pwm_lpss_apply()
201 		pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);  in pwm_lpss_apply()
208 static int pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,  in pwm_lpss_get_state()  argument
218 	base_unit_range = BIT(lpwm->info->base_unit_bits);  in pwm_lpss_get_state()
220 	ctrl = pwm_lpss_read(pwm);  in pwm_lpss_get_state()
221 	on_time_div = 255 - (ctrl & PWM_ON_TIME_DIV_MASK);  in pwm_lpss_get_state()
222 	base_unit = (ctrl >> PWM_BASE_UNIT_SHIFT) & (base_unit_range - 1);  in pwm_lpss_get_state()
224 	freq = base_unit * lpwm->info->clk_rate;  in pwm_lpss_get_state()
227 		state->period = NSEC_PER_SEC;  in pwm_lpss_get_state()
229 		state->period = NSEC_PER_SEC / (unsigned long)freq;  in pwm_lpss_get_state()
231 	on_time_div *= state->period;  in pwm_lpss_get_state()
233 	state->duty_cycle = on_time_div;  in pwm_lpss_get_state()
235 	state->polarity = PWM_POLARITY_NORMAL;  in pwm_lpss_get_state()
236 	state->enabled = !!(ctrl & PWM_ENABLE);  in pwm_lpss_get_state()
257 	if (WARN_ON(info->npwm > LPSS_MAX_PWMS))  in devm_pwm_lpss_probe()
258 		return ERR_PTR(-ENODEV);  in devm_pwm_lpss_probe()
260 	chip = devm_pwmchip_alloc(dev, info->npwm, sizeof(*lpwm));  in devm_pwm_lpss_probe()
265 	lpwm->regs = base;  in devm_pwm_lpss_probe()
266 	lpwm->info = info;  in devm_pwm_lpss_probe()
268 	c = lpwm->info->clk_rate;  in devm_pwm_lpss_probe()
270 		return ERR_PTR(-EINVAL);  in devm_pwm_lpss_probe()
272 	chip->ops = &pwm_lpss_ops;  in devm_pwm_lpss_probe()
276 		dev_err(dev, "failed to add PWM chip: %d\n", ret);  in devm_pwm_lpss_probe()
280 	for (i = 0; i < lpwm->info->npwm; i++) {  in devm_pwm_lpss_probe()
281 		ctrl = pwm_lpss_read(&chip->pwms[i]);  in devm_pwm_lpss_probe()
290 MODULE_DESCRIPTION("PWM driver for Intel LPSS");