1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (c) 2014-2015, Imagination Technologies
7  * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
19 #include <linux/pwm.h>
23 /* PWM registers */
43  * PWM period is specified with a timebase register,
44  * in number of step periods. The PWM duty cycle is also
49  * Imposing a minimum timebase, will impose a maximum PWM frequency.
81 	writel(val, imgchip->base + reg);  in img_pwm_writel()
86 	return readl(imgchip->base + reg);  in img_pwm_readl()
89 static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,  in img_pwm_config()  argument
95 	unsigned int max_timebase = imgchip->data->max_timebase;  in img_pwm_config()
98 	if (period_ns < imgchip->min_period_ns ||  in img_pwm_config()
99 	    period_ns > imgchip->max_period_ns) {  in img_pwm_config()
101 		return -ERANGE;  in img_pwm_config()
104 	input_clk_hz = clk_get_rate(imgchip->pwm_clk);  in img_pwm_config()
123 		return -EINVAL;  in img_pwm_config()
133 	val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));  in img_pwm_config()
135 		PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);  in img_pwm_config()
140 	img_pwm_writel(imgchip, PWM_CH_CFG(pwm->hwpwm), val);  in img_pwm_config()
148 static int img_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)  in img_pwm_enable()  argument
159 	val |= BIT(pwm->hwpwm);  in img_pwm_enable()
162 	regmap_clear_bits(imgchip->periph_regs, PERIP_PWM_PDM_CONTROL,  in img_pwm_enable()
164 			  PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm));  in img_pwm_enable()
169 static void img_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)  in img_pwm_disable()  argument
175 	val &= ~BIT(pwm->hwpwm);  in img_pwm_disable()
182 static int img_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,  in img_pwm_apply()  argument
187 	if (state->polarity != PWM_POLARITY_NORMAL)  in img_pwm_apply()
188 		return -EINVAL;  in img_pwm_apply()
190 	if (!state->enabled) {  in img_pwm_apply()
191 		if (pwm->state.enabled)  in img_pwm_apply()
192 			img_pwm_disable(chip, pwm);  in img_pwm_apply()
197 	err = img_pwm_config(chip, pwm, state->duty_cycle, state->period);  in img_pwm_apply()
201 	if (!pwm->state.enabled)  in img_pwm_apply()
202 		err = img_pwm_enable(chip, pwm);  in img_pwm_apply()
217 		.compatible = "img,pistachio-pwm",
229 	clk_disable_unprepare(imgchip->pwm_clk);  in img_pwm_runtime_suspend()
230 	clk_disable_unprepare(imgchip->sys_clk);  in img_pwm_runtime_suspend()
241 	ret = clk_prepare_enable(imgchip->sys_clk);  in img_pwm_runtime_resume()
247 	ret = clk_prepare_enable(imgchip->pwm_clk);  in img_pwm_runtime_resume()
249 		dev_err(dev, "could not prepare or enable pwm clock\n");  in img_pwm_runtime_resume()
250 		clk_disable_unprepare(imgchip->sys_clk);  in img_pwm_runtime_resume()
265 	chip = devm_pwmchip_alloc(&pdev->dev, IMG_PWM_NPWM, sizeof(*imgchip));  in img_pwm_probe()
270 	imgchip->base = devm_platform_ioremap_resource(pdev, 0);  in img_pwm_probe()
271 	if (IS_ERR(imgchip->base))  in img_pwm_probe()
272 		return PTR_ERR(imgchip->base);  in img_pwm_probe()
274 	imgchip->data = device_get_match_data(&pdev->dev);  in img_pwm_probe()
276 	imgchip->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,  in img_pwm_probe()
277 							       "img,cr-periph");  in img_pwm_probe()
278 	if (IS_ERR(imgchip->periph_regs))  in img_pwm_probe()
279 		return PTR_ERR(imgchip->periph_regs);  in img_pwm_probe()
281 	imgchip->sys_clk = devm_clk_get(&pdev->dev, "sys");  in img_pwm_probe()
282 	if (IS_ERR(imgchip->sys_clk)) {  in img_pwm_probe()
283 		dev_err(&pdev->dev, "failed to get system clock\n");  in img_pwm_probe()
284 		return PTR_ERR(imgchip->sys_clk);  in img_pwm_probe()
287 	imgchip->pwm_clk = devm_clk_get(&pdev->dev, "pwm");  in img_pwm_probe()
288 	if (IS_ERR(imgchip->pwm_clk)) {  in img_pwm_probe()
289 		dev_err(&pdev->dev, "failed to get pwm clock\n");  in img_pwm_probe()
290 		return PTR_ERR(imgchip->pwm_clk);  in img_pwm_probe()
295 	pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT);  in img_pwm_probe()
296 	pm_runtime_use_autosuspend(&pdev->dev);  in img_pwm_probe()
297 	pm_runtime_enable(&pdev->dev);  in img_pwm_probe()
298 	if (!pm_runtime_enabled(&pdev->dev)) {  in img_pwm_probe()
299 		ret = img_pwm_runtime_resume(&pdev->dev);  in img_pwm_probe()
304 	clk_rate = clk_get_rate(imgchip->pwm_clk);  in img_pwm_probe()
306 		dev_err(&pdev->dev, "imgchip clock has no frequency\n");  in img_pwm_probe()
307 		ret = -EINVAL;  in img_pwm_probe()
312 	val = (u64)NSEC_PER_SEC * 512 * imgchip->data->max_timebase;  in img_pwm_probe()
314 	imgchip->max_period_ns = val;  in img_pwm_probe()
318 	imgchip->min_period_ns = val;  in img_pwm_probe()
320 	chip->ops = &img_pwm_ops;  in img_pwm_probe()
324 		dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);  in img_pwm_probe()
331 	if (!pm_runtime_enabled(&pdev->dev))  in img_pwm_probe()
332 		img_pwm_runtime_suspend(&pdev->dev);  in img_pwm_probe()
334 	pm_runtime_disable(&pdev->dev);  in img_pwm_probe()
335 	pm_runtime_dont_use_autosuspend(&pdev->dev);  in img_pwm_probe()
343 	pm_runtime_disable(&pdev->dev);  in img_pwm_remove()
344 	if (!pm_runtime_status_suspended(&pdev->dev))  in img_pwm_remove()
345 		img_pwm_runtime_suspend(&pdev->dev);  in img_pwm_remove()
363 	for (i = 0; i < chip->npwm; i++)  in img_pwm_suspend()
364 		imgchip->suspend_ch_cfg[i] = img_pwm_readl(imgchip,  in img_pwm_suspend()
367 	imgchip->suspend_ctrl_cfg = img_pwm_readl(imgchip, PWM_CTRL_CFG);  in img_pwm_suspend()
385 	for (i = 0; i < chip->npwm; i++)  in img_pwm_resume()
387 			       imgchip->suspend_ch_cfg[i]);  in img_pwm_resume()
389 	img_pwm_writel(imgchip, PWM_CTRL_CFG, imgchip->suspend_ctrl_cfg);  in img_pwm_resume()
391 	for (i = 0; i < chip->npwm; i++)  in img_pwm_resume()
392 		if (imgchip->suspend_ctrl_cfg & BIT(i))  in img_pwm_resume()
393 			regmap_clear_bits(imgchip->periph_regs,  in img_pwm_resume()
414 		.name = "img-pwm",
424 MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver");