Lines Matching +full:0 +full:x390000
28 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
29 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
31 #define PCI_VENDOR_ID_CELESTICA 0x18d4
32 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
34 #define PCI_VENDOR_ID_OROLIA 0x1ad7
35 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000
37 #define PCI_VENDOR_ID_ADVA 0xad5a
38 #define PCI_DEVICE_ID_ADVA_TIMECARD 0x0400
76 #define OCP_CTRL_ENABLE BIT(0)
84 #define OCP_STATUS_IN_SYNC BIT(0)
87 #define OCP_SELECT_CLK_NONE 0
88 #define OCP_SELECT_CLK_REG 0xfe
106 #define TOD_CTRL_ENABLE BIT(0)
107 #define TOD_CTRL_GNSS_MASK GENMASK(3, 0)
110 #define TOD_STATUS_UTC_MASK GENMASK(7, 0)
141 #define PPS_STATUS_FILTER_ERR BIT(0)
164 #define IRIG_M_CTRL_ENABLE BIT(0)
175 #define IRIG_S_CTRL_ENABLE BIT(0)
185 #define DCF_M_CTRL_ENABLE BIT(0)
195 #define DCF_S_CTRL_ENABLE BIT(0)
229 #define FREQ_STATUS_MASK GENMASK(23, 0)
296 #define OCP_CAP_BASIC BIT(0)
387 #define OCP_REQ_TIMESTAMP BIT(0)
441 { EEPROM_ENTRY(0x43, board_id) },
442 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },
447 { EEPROM_ENTRY(0x200 + 0x43, board_id) },
448 { EEPROM_ENTRY(0x200 + 0x63, serial) },
476 * 0: PPS (TS5)
505 .offset = 0x01000000, .size = 0x10000,
509 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
511 .index = 0,
518 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
527 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
536 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
545 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
555 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
563 OCP_EXT_RESOURCE(signal_out[0]),
564 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
573 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
582 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
591 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
600 .offset = 0x01030000, .size = 0x10000,
604 .offset = 0x01040000, .size = 0x10000,
608 .offset = 0x01050000, .size = 0x10000,
612 .offset = 0x01070000, .size = 0x10000,
616 .offset = 0x01080000, .size = 0x10000,
620 .offset = 0x01090000, .size = 0x10000,
624 .offset = 0x010A0000, .size = 0x10000,
628 .offset = 0x010B0000, .size = 0x10000,
632 .offset = 0x00020000, .size = 0x1000,
636 .offset = 0x00130000, .size = 0x1000,
640 .offset = 0x00140000, .size = 0x1000,
644 .offset = 0x00220000, .size = 0x1000,
648 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
656 { I2C_BOARD_INFO("24c02", 0x50) },
657 { I2C_BOARD_INFO("24mac402", 0x58),
665 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
672 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
679 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
686 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
690 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
692 .name = "xilinx_spi", .pci_offset = 0,
706 OCP_MEM_RESOURCE(freq_in[0]),
707 .offset = 0x01200000, .size = 0x10000,
711 .offset = 0x01210000, .size = 0x10000,
715 .offset = 0x01220000, .size = 0x10000,
719 .offset = 0x01230000, .size = 0x10000,
724 .servo_offset_p = 0x2000,
725 .servo_offset_i = 0x1000,
726 .servo_drift_p = 0,
727 .servo_drift_i = 0,
746 .offset = 0x01000000, .size = 0x10000,
750 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
757 .offset = 0x003C0000, .size = 0x1000,
762 .offset = 0x360000, .size = 0x20, .irq_vec = 12,
764 .index = 0,
771 .offset = 0x380000, .size = 0x20, .irq_vec = 8,
780 .offset = 0x390000, .size = 0x20, .irq_vec = 10,
789 .offset = 0x3A0000, .size = 0x20, .irq_vec = 14,
798 .offset = 0x3B0000, .size = 0x20, .irq_vec = 15,
808 .offset = 0x00330000, .size = 0x20, .irq_vec = 11,
817 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
819 .name = "spi_altera", .pci_offset = 0,
832 .offset = 0x350000, .size = 0x100, .irq_vec = 4,
842 I2C_BOARD_INFO("24c08", 0x50),
849 .offset = 0x00190000, .irq_vec = 7,
856 .offset = 0x210000, .size = 0x1000,
861 .servo_offset_p = 0x2000,
862 .servo_offset_i = 0x1000,
863 .servo_drift_p = 0,
864 .servo_drift_i = 0,
873 .offset = 0x01000000, .size = 0x10000,
877 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
879 .index = 0,
886 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
895 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
905 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
913 OCP_EXT_RESOURCE(signal_out[0]),
914 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
923 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
932 .offset = 0x01030000, .size = 0x10000,
936 .offset = 0x01040000, .size = 0x10000,
940 .offset = 0x01050000, .size = 0x10000,
944 .offset = 0x00020000, .size = 0x1000,
948 .offset = 0x00130000, .size = 0x1000,
952 .offset = 0x00140000, .size = 0x1000,
956 .offset = 0x00220000, .size = 0x1000,
960 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
967 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
973 OCP_MEM_RESOURCE(freq_in[0]),
974 .offset = 0x01200000, .size = 0x10000,
978 .offset = 0x01210000, .size = 0x10000,
982 .offset = 0x00310400, .size = 0x10000, .irq_vec = 9,
984 .name = "spi_altera", .pci_offset = 0,
997 .offset = 0x150000, .size = 0x100, .irq_vec = 7,
1009 { I2C_BOARD_INFO("24c02", 0x50) },
1010 { I2C_BOARD_INFO("24mac402", 0x58),
1019 .servo_offset_p = 0xc000,
1020 .servo_offset_i = 0x1000,
1021 .servo_drift_p = 0,
1022 .servo_drift_i = 0,
1047 { .name = "NONE", .value = 0 },
1054 { .name = "REGS", .value = 0xfe },
1055 { .name = "EXT", .value = 0xff },
1061 #define SMA_SELECT_MASK GENMASK(14, 0)
1064 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1065 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1066 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1067 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1068 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1069 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1070 { .name = "DCF", .value = 0x0020, .frequency = 77500 },
1071 { .name = "TS3", .value = 0x0040, .frequency = 0 },
1072 { .name = "TS4", .value = 0x0080, .frequency = 0 },
1073 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1074 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1075 { .name = "FREQ3", .value = 0x0400, .frequency = 0 },
1076 { .name = "FREQ4", .value = 0x0800, .frequency = 0 },
1077 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1082 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1083 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1084 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1085 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1086 { .name = "GNSS2", .value = 0x0008, .frequency = 1 },
1087 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1088 { .name = "DCF", .value = 0x0020, .frequency = 77000 },
1089 { .name = "GEN1", .value = 0x0040 },
1090 { .name = "GEN2", .value = 0x0080 },
1091 { .name = "GEN3", .value = 0x0100 },
1092 { .name = "GEN4", .value = 0x0200 },
1093 { .name = "GND", .value = 0x2000 },
1094 { .name = "VCC", .value = 0x4000 },
1099 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1100 { .name = "10Mhz", .value = 0x0008, .frequency = 1000000 },
1105 { .name = "PHC", .value = 0x0002, .frequency = 1 },
1106 { .name = "GNSS", .value = 0x0004, .frequency = 1 },
1107 { .name = "10Mhz", .value = 0x0010, .frequency = 10000000 },
1112 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1113 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1114 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1115 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1116 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1117 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1118 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1119 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1124 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1125 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1126 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1127 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1128 { .name = "GEN1", .value = 0x0040 },
1129 { .name = "GEN2", .value = 0x0080 },
1130 { .name = "GND", .value = 0x2000 },
1131 { .name = "VCC", .value = 0x4000 },
1172 for (i = 0; tbl[i].name; i++) in ptp_ocp_select_name_from_val()
1184 for (i = 0; tbl[i].name; i++) { in ptp_ocp_select_val_from_name()
1198 count = 0; in ptp_ocp_select_table_show()
1199 for (i = 0; tbl[i].name; i++) in ptp_ocp_select_table_show()
1219 for (i = 0; i < 100; i++) { in __ptp_ocp_gettime_locked()
1238 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT; in __ptp_ocp_gettime_locked()
1288 return 0; in ptp_ocp_settime()
1335 return 0; in ptp_ocp_adjtime()
1338 sign = delta_ns < 0 ? BIT(31) : 0; in ptp_ocp_adjtime()
1345 return 0; in ptp_ocp_adjtime()
1351 if (scaled_ppm == 0) in ptp_ocp_null_adjfine()
1352 return 0; in ptp_ocp_null_adjfine()
1360 return 0; in ptp_ocp_null_getmaxphase()
1382 case 0: in ptp_ocp_enable()
1408 case 0: in ptp_ocp_enable()
1413 rq->perout.period.nsec != 0)) in ptp_ocp_enable()
1415 return 0; in ptp_ocp_enable()
1452 return 0; in ptp_ocp_verify()
1454 /* channel 0 is 1PPS from PHC. in ptp_ocp_verify()
1494 iowrite32(0, &bp->reg->drift_ns); in __ptp_ocp_clear_drift_locked()
1541 bp->gnss_lost = 0; in ptp_ocp_watchdog()
1565 for (i = 0; i < 3; i++) { in ptp_ocp_estimate_pci_timing()
1601 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) { in ptp_ocp_init_clock()
1616 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0); in ptp_ocp_init_clock()
1620 return 0; in ptp_ocp_init_clock()
1681 return 0; in ptp_ocp_nvmem_match()
1686 return 0; in ptp_ocp_nvmem_match()
1780 NULL, 0, 0); in ptp_ocp_devlink_fw_image()
1788 NULL, 0, 0); in ptp_ocp_devlink_fw_image()
1797 NULL, 0, 0); in ptp_ocp_devlink_fw_image()
1801 crc = crc16(0xffff, &fw->data[offset], length); in ptp_ocp_devlink_fw_image()
1805 NULL, 0, 0); in ptp_ocp_devlink_fw_image()
1812 return 0; in ptp_ocp_devlink_fw_image()
1831 off = 0; in ptp_ocp_devlink_flash()
1876 NULL, 0, 0); in ptp_ocp_devlink_flash_update()
1881 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0); in ptp_ocp_devlink_flash_update()
1905 return 0; in ptp_ocp_devlink_info_get()
1919 return 0; in ptp_ocp_devlink_info_get()
1940 start = pci_resource_start(bp->pdev, 0) + r->offset; in ptp_ocp_get_mem()
1954 start = pci_resource_start(pdev, 0) + r->offset; in ptp_ocp_register_spi()
1955 res[0] = DEFINE_RES_MEM(start, r->size); in ptp_ocp_register_spi()
1970 return 0; in ptp_ocp_register_spi()
1981 start = pci_resource_start(pdev, 0) + r->offset; in ptp_ocp_i2c_bus()
1982 res[0] = DEFINE_RES_MEM(start, r->size); in ptp_ocp_i2c_bus()
2004 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0, in ptp_ocp_register_i2c()
2018 return 0; in ptp_ocp_register_i2c()
2038 iowrite32(0, ®->intr_mask); in ptp_ocp_signal_irq()
2039 iowrite32(0, ®->enable); in ptp_ocp_signal_irq()
2043 iowrite32(0, ®->intr); /* ack interrupt */ in ptp_ocp_signal_irq()
2057 return 0; in ptp_ocp_signal_set()
2084 return 0; in ptp_ocp_signal_set()
2096 return 0; in ptp_ocp_signal_from_perout()
2122 iowrite32(0, ®->intr_mask); in ptp_ocp_signal_enable()
2123 iowrite32(0, ®->enable); in ptp_ocp_signal_enable()
2126 return 0; in ptp_ocp_signal_enable()
2141 iowrite32(0, ®->repeat_count); in ptp_ocp_signal_enable()
2143 iowrite32(0, ®->intr); /* clear interrupt state */ in ptp_ocp_signal_enable()
2149 return 0; in ptp_ocp_signal_enable()
2166 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0) in ptp_ocp_ts_irq()
2202 if ((!!old_map ^ !!bp->pps_req_map) == 0) in ptp_ocp_ts_enable()
2203 return 0; in ptp_ocp_ts_enable()
2211 iowrite32(0, ®->intr_mask); in ptp_ocp_ts_enable()
2212 iowrite32(0, ®->enable); in ptp_ocp_ts_enable()
2215 return 0; in ptp_ocp_ts_enable()
2221 ext->info->enable(ext, ~0, false); in ptp_ocp_unregister_ext()
2256 return 0; in ptp_ocp_register_ext()
2272 memset(&uart, 0, sizeof(uart)); in ptp_ocp_serial_line()
2276 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset; in ptp_ocp_serial_line()
2292 if (port.line < 0) in ptp_ocp_register_serial()
2300 return 0; in ptp_ocp_register_serial()
2314 return 0; in ptp_ocp_register_mem()
2323 iowrite32(0, &bp->nmea_out->ctrl); /* disable */ in ptp_ocp_nmea_out_init()
2333 iowrite32(0, ®->enable); /* disable */ in _ptp_ocp_signal_init()
2345 for (i = 0; i < 4; i++) in ptp_ocp_signal_init()
2365 count = 0; in ptp_ocp_attr_group_add()
2366 for (i = 0; attr_tbl[i].cap; i++) in ptp_ocp_attr_group_add()
2375 count = 0; in ptp_ocp_attr_group_add()
2376 for (i = 0; attr_tbl[i].cap; i++) in ptp_ocp_attr_group_add()
2382 bp->attr_group[0] = NULL; in ptp_ocp_attr_group_add()
2397 ctrl |= enable ? bit : 0; in ptp_ocp_enable_fpga()
2433 ptp_ocp_irig_out(bp, val & 0x00100010); in __handle_signal_outputs()
2434 ptp_ocp_dcf_out(bp, val & 0x00200020); in __handle_signal_outputs()
2440 ptp_ocp_irig_in(bp, val & 0x00100010); in __handle_signal_inputs()
2441 ptp_ocp_dcf_in(bp, val & 0x00200020); in __handle_signal_inputs()
2457 shift = sma_nr & 1 ? 0 : 16; in ptp_ocp_sma_fb_get()
2459 return (ioread32(gpio) >> shift) & 0xffff; in ptp_ocp_sma_fb_get()
2470 shift = sma_nr & 1 ? 0 : 16; in ptp_ocp_sma_fb_set_output()
2472 mask = 0xffff << (16 - shift); in ptp_ocp_sma_fb_set_output()
2485 return 0; in ptp_ocp_sma_fb_set_output()
2496 shift = sma_nr & 1 ? 0 : 16; in ptp_ocp_sma_fb_set_inputs()
2498 mask = 0xffff << (16 - shift); in ptp_ocp_sma_fb_set_inputs()
2511 return 0; in ptp_ocp_sma_fb_set_inputs()
2529 for (i = 0; i < OCP_SMA_NUM; i++) { in ptp_ocp_sma_fb_init()
2535 bp->sma[0].mode = SMA_MODE_IN; in ptp_ocp_sma_fb_init()
2541 for (i = 0; i < OCP_SMA_NUM; i++) { in ptp_ocp_sma_fb_init()
2554 if (reg == 0xffffffff) { in ptp_ocp_sma_fb_init()
2555 for (i = 0; i < OCP_SMA_NUM; i++) in ptp_ocp_sma_fb_init()
2559 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT; in ptp_ocp_sma_fb_init()
2594 for (i = 0; i < 4; i++) { in ptp_ocp_set_pins()
2602 return 0; in ptp_ocp_set_pins()
2614 if ((version & 0xffff) == 0) { in ptp_ocp_fb_set_version()
2620 bp->fw_version = version & 0x7fff; in ptp_ocp_fb_set_version()
2681 int err = 0; in ptp_ocp_register_resources()
2704 .capabilities = 0, in ptp_ocp_art_sma_init()
2713 bp->sma[0].mode = SMA_MODE_IN; in ptp_ocp_art_sma_init()
2718 bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */ in ptp_ocp_art_sma_init()
2719 bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */ in ptp_ocp_art_sma_init()
2720 bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */ in ptp_ocp_art_sma_init()
2721 bp->sma[3].default_fcn = 0x02; /* OUT: PHC */ in ptp_ocp_art_sma_init()
2723 for (i = 0; i < OCP_SMA_NUM; i++) { in ptp_ocp_art_sma_init()
2735 switch (reg & 0xff) { in ptp_ocp_art_sma_init()
2736 case 0: in ptp_ocp_art_sma_init()
2761 return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff; in ptp_ocp_art_sma_get()
2764 /* note: store 0 is considered invalid. */
2770 int err = 0; in ptp_ocp_art_sma_set()
2781 if (((reg >> 16) & val) == 0) { in ptp_ocp_art_sma_set()
2784 reg = (reg & 0xff00) | (val & 0xff); in ptp_ocp_art_sma_set()
2806 bp->flash_start = 0x1000000; in ptp_ocp_art_board_init()
2835 bp->flash_start = 0xA00000; in ptp_ocp_adva_board_init()
2841 if ((version & 0xffff) == 0) { in ptp_ocp_adva_board_init()
2846 bp->fw_version = version & 0xffff; in ptp_ocp_adva_board_init()
2889 for (i = 0; tbl[i].name; i++) { in ptp_ocp_show_inputs()
2895 if (!val && def_val >= 0) { in ptp_ocp_show_inputs()
2921 idx = 0; in sma_parse_inputs()
2922 dir = *mode == SMA_MODE_IN ? 0 : 1; in sma_parse_inputs()
2923 if (!strcasecmp("IN:", argv[0])) { in sma_parse_inputs()
2924 dir = 0; in sma_parse_inputs()
2927 if (!strcasecmp("OUT:", argv[0])) { in sma_parse_inputs()
2931 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT; in sma_parse_inputs()
2933 ret = 0; in sma_parse_inputs()
2936 if (ret < 0) in sma_parse_inputs()
2958 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val); in ptp_ocp_sma_show()
2969 return ptp_ocp_sma_show(bp, 1, buf, 0, 1); in sma1_show()
2985 return ptp_ocp_sma_show(bp, 3, buf, -1, 0); in sma3_show()
3007 return 0; in ptp_ocp_sma_store_val()
3014 ptp_ocp_sma_set_output(bp, sma_nr, 0); in ptp_ocp_sma_store_val()
3016 ptp_ocp_sma_set_inputs(bp, sma_nr, 0); in ptp_ocp_sma_store_val()
3024 val = 0; in ptp_ocp_sma_store_val()
3043 if (val < 0) in ptp_ocp_sma_store()
3102 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf); in available_sma_inputs_show()
3155 err = kstrtou64(argv[argc], 0, &s.phase); in signal_store()
3161 err = kstrtoint(argv[argc], 0, &s.duty); in signal_store()
3167 err = kstrtou64(argv[argc], 0, &s.period); in signal_store()
3179 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0); in signal_store()
3207 static EXT_ATTR_RW(signal, signal, 0);
3221 static EXT_ATTR_RO(signal, duty, 0);
3235 static EXT_ATTR_RO(signal, period, 0);
3249 static EXT_ATTR_RO(signal, phase, 0);
3264 static EXT_ATTR_RO(signal, polarity, 0);
3278 static EXT_ATTR_RO(signal, running, 0);
3294 static EXT_ATTR_RO(signal, start, 0);
3309 err = kstrtou32(buf, 0, &val); in seconds_store()
3312 if (val > 0xff) in seconds_store()
3316 val = (val << 8) | 0x1; in seconds_store()
3333 val = (val >> 8) & 0xff; in seconds_show()
3335 val = 0; in seconds_show()
3339 static EXT_ATTR_RW(freq, seconds, 0);
3359 return 0; in frequency_show()
3361 static EXT_ATTR_RO(freq, frequency, 0);
3389 return port->line == -1 ? 0 : 0444; in ptp_ocp_timecard_tty_is_visible()
3459 err = kstrtou32(buf, 0, &val); in utc_tai_offset_store()
3487 err = kstrtou32(buf, 0, &val); in ts_window_adjust_store()
3504 val = (val >> 16) & 0x07; in irig_b_mode_show()
3519 err = kstrtou8(buf, 0, &val); in irig_b_mode_store()
3525 reg = ((val & 0x7) << 16); in irig_b_mode_store()
3528 iowrite32(0, &bp->irig_out->ctrl); /* disable */ in irig_b_mode_store()
3559 if (val < 0) in clock_source_store()
3629 u32 val = 0; in tod_correction_store()
3631 err = kstrtos32(buf, 0, &res); in tod_correction_store()
3634 if (res < 0) { in tod_correction_store()
3668 DEVICE_SIGNAL_GROUP(gen1, 0);
3688 DEVICE_FREQ_GROUP(freq1, 0);
3708 err = 0; in disciplining_config_read()
3745 err = nvmem_device_write(nvmem, 0x00, count, buf); in disciplining_config_write()
3770 err = 0; in temperature_table_read()
3778 err = nvmem_device_read(nvmem, 0x90 + off, count, buf); in temperature_table_read()
3807 err = nvmem_device_write(nvmem, 0x90, count, buf); in temperature_table_write()
3925 for (i = 0; i < 4; i++) { in gpio_input_map()
3928 if (map[i][0] & (1 << bit)) { in gpio_input_map()
3945 for (i = 0; i < 4; i++) { in gpio_output_map()
3994 val = (val >> 8) & 0xff; in _frequency_summary_show()
4031 for (i = 0; i < __PORT_COUNT; i++) { in ptp_ocp_summary_show()
4037 memset(sma_val, 0xff, sizeof(sma_val)); in ptp_ocp_summary_show()
4042 sma_val[0][0] = reg & 0xffff; in ptp_ocp_summary_show()
4043 sma_val[1][0] = reg >> 16; in ptp_ocp_summary_show()
4046 sma_val[2][1] = reg & 0xffff; in ptp_ocp_summary_show()
4050 sma_val[2][0] = reg & 0xffff; in ptp_ocp_summary_show()
4051 sma_val[3][0] = reg >> 16; in ptp_ocp_summary_show()
4054 sma_val[0][1] = reg & 0xffff; in ptp_ocp_summary_show()
4060 sma_val[0][0], sma_val[0][1], buf); in ptp_ocp_summary_show()
4064 sma_val[1][0], sma_val[1][1], buf); in ptp_ocp_summary_show()
4068 sma_val[2][0], sma_val[2][1], buf); in ptp_ocp_summary_show()
4072 sma_val[3][0], sma_val[3][1], buf); in ptp_ocp_summary_show()
4128 for (i = 0; i < 4; i++) in ptp_ocp_summary_show()
4132 for (i = 0; i < 4; i++) in ptp_ocp_summary_show()
4180 if (val & 0x01) { in ptp_ocp_summary_show()
4181 gpio_input_map(src, bp, sma_val, 0, NULL); in ptp_ocp_summary_show()
4183 } else if (val & 0x02) { in ptp_ocp_summary_show()
4185 } else if (val & 0x04) { in ptp_ocp_summary_show()
4203 case 0: in ptp_ocp_summary_show()
4243 return 0; in ptp_ocp_summary_show()
4260 return 0; in ptp_ocp_tod_status_show()
4262 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val); in ptp_ocp_tod_status_show()
4264 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0; in ptp_ocp_tod_status_show()
4273 val >> 24, (val >> 16) & 0xff, val & 0xffff); in ptp_ocp_tod_status_show()
4276 seq_printf(s, "Status register: 0x%08X\n", val); in ptp_ocp_tod_status_show()
4284 seq_printf(s, "UTC status register: 0x%08X\n", val); in ptp_ocp_tod_status_show()
4286 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0); in ptp_ocp_tod_status_show()
4288 val & TOD_STATUS_LEAP_VALID ? 1 : 0, in ptp_ocp_tod_status_show()
4289 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0); in ptp_ocp_tod_status_show()
4294 return 0; in ptp_ocp_tod_status_show()
4348 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL); in ptp_ocp_device_init()
4350 if (err < 0) { in ptp_ocp_device_init()
4359 for (i = 0; i < __PORT_COUNT; i++) in ptp_ocp_device_init()
4379 return 0; in ptp_ocp_device_init()
4427 return 0; in ptp_ocp_complete()
4439 version >> 24, (version >> 16) & 0xff, version & 0xffff, in ptp_ocp_phc_info()
4470 for (i = 0; i < __PORT_COUNT; i++) { in ptp_ocp_info()
4514 for (i = 0; i < 4; i++) in ptp_ocp_detach()
4517 for (i = 0; i < __PORT_COUNT; i++) in ptp_ocp_detach()
4542 return 0; in ptp_ocp_dpll_lock_status_get()
4557 return 0; in ptp_ocp_dpll_state_get()
4567 return 0; in ptp_ocp_dpll_mode_get()
4582 return 0; in ptp_ocp_dpll_direction_get()
4601 return ptp_ocp_sma_store_val(bp, 0, mode, sma_nr + 1); in ptp_ocp_dpll_direction_set()
4620 for (i = 0; tbl[i].name; i++) in ptp_ocp_dpll_frequency_set()
4641 for (i = 0; tbl[i].name; i++) in ptp_ocp_dpll_frequency_get()
4644 return 0; in ptp_ocp_dpll_frequency_get()
4713 if (err < 0) { in ptp_ocp_probe()
4740 bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE); in ptp_ocp_probe()
4751 for (i = 0; i < OCP_SMA_NUM; i++) { in ptp_ocp_probe()
4767 return 0; in ptp_ocp_probe()
4792 for (i = 0; i < OCP_SMA_NUM; i++) { in ptp_ocp_remove()
4828 return 0; in ptp_ocp_i2c_notifier_call()
4832 return 0; in ptp_ocp_i2c_notifier_call()
4838 return 0; in ptp_ocp_i2c_notifier_call()
4847 return 0; in ptp_ocp_i2c_notifier_call()
4877 return 0; in ptp_ocp_init()