Lines Matching +full:mode +full:- +full:reg
1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
5 * Copyright (C) 2016-2018 Mellanox Technologies
6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com>
12 #include <linux/i2c-mux.h>
17 #include <linux/platform_data/i2c-mux-reg.h>
297 #define MLXPLAT_CPLD_NR_NONE -1
341 /* mlxplat_priv - platform private data
342 * @pdev_i2c - i2c controller platform device
343 * @pdev_mux - array of mux platform devices
344 * @pdev_hotplug - hotplug platform devices
345 * @pdev_led - led platform devices
346 * @pdev_io_regs - register access platform devices
347 * @pdev_fan - FAN platform devices
348 * @pdev_wd - array of watchdog platform devices
393 .reg = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
438 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
446 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
465 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
473 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3,
481 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
502 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG4,
512 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
522 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3,
532 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
551 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
561 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
582 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
592 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
648 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
654 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
664 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
670 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
679 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
686 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
696 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
702 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
711 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
718 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
728 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
735 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
742 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
749 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
759 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
768 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET,
778 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
787 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
796 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
805 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
817 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
826 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
835 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
844 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
866 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
875 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
884 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
915 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
921 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
932 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
941 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
963 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
969 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
978 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
985 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
995 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1001 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1007 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1013 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1023 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1032 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1041 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1050 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1072 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1078 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1088 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1097 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1119 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1125 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1134 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1142 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1150 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1158 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1166 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1174 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1182 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1194 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1203 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1212 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1221 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1243 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1249 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1255 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1261 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1270 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1277 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1284 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1291 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1302 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1312 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1322 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1331 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1340 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET,
1352 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1362 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1372 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1381 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1412 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1419 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1426 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1433 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1448 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1456 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1460 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1464 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1468 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1472 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1476 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1480 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1484 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1519 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1529 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1539 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1549 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1559 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1569 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1579 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1589 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1602 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1616 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1630 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1644 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1658 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1672 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1686 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1700 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1717 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1727 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1737 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1747 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1757 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1767 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1777 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1787 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1800 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1810 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1820 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1830 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1840 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1850 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1860 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1870 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1883 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1893 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1903 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1913 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1923 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1933 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1943 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1953 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1966 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
1976 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
1986 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
1996 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
2006 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
2016 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
2026 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
2036 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
2049 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2059 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2069 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2079 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2089 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2099 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2109 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2119 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2133 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
2143 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
2153 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
2162 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
2172 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
2182 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
2192 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
2202 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
2212 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
2222 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
2232 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2254 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET,
2264 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET,
2286 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET,
2292 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET,
2301 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET,
2307 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET,
2317 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
2327 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
2337 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
2346 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET,
2355 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET,
2379 dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button"); in mlxplat_mlxcpld_l1_switch_pwr_events_handler()
2394 .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET,
2411 err = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ®val); in mlxplat_mlxcpld_l1_switch_intrusion_events_handler()
2416 dev_info(&mlxplat_dev->dev, "Detected intrusion - system latch is opened"); in mlxplat_mlxcpld_l1_switch_intrusion_events_handler()
2417 err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, in mlxplat_mlxcpld_l1_switch_intrusion_events_handler()
2420 dev_info(&mlxplat_dev->dev, "System latch is properly closed"); in mlxplat_mlxcpld_l1_switch_intrusion_events_handler()
2421 err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, in mlxplat_mlxcpld_l1_switch_intrusion_events_handler()
2432 dev_err(&mlxplat_dev->dev, "Register access failed"); in mlxplat_mlxcpld_l1_switch_intrusion_events_handler()
2443 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET,
2449 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET,
2455 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET,
2463 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET,
2473 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
2482 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET,
2491 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET,
2500 .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET,
2509 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET,
2532 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2537 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2542 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2547 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2552 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2557 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2562 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2567 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2572 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2577 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2582 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2587 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2601 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2606 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2611 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2616 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2630 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2635 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2649 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2654 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2659 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2664 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2669 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2674 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2679 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2684 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2689 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
2703 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2708 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2713 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2718 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2723 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2730 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2737 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2744 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2751 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2758 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2765 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2772 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2779 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2786 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2793 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2800 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2807 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
2814 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
2821 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
2835 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2840 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2845 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2850 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2855 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2860 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2865 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2870 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2875 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2880 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2885 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2890 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2895 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
2909 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2914 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2919 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2924 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2929 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2936 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2943 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2950 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2957 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2964 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2971 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2978 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2985 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2992 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2999 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
3006 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
3013 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
3020 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
3027 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
3032 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
3037 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
3042 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET,
3047 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET,
3061 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
3066 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
3071 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
3078 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
3085 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
3092 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
3099 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
3106 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
3113 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
3120 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
3127 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
3134 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
3141 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
3148 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
3155 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
3169 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
3171 .mode = 0444,
3175 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
3177 .mode = 0444,
3181 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
3183 .mode = 0444,
3188 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
3190 .mode = 0444,
3195 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
3197 .mode = 0444,
3201 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
3203 .mode = 0444,
3207 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3209 .mode = 0444,
3213 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3215 .mode = 0444,
3219 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3221 .mode = 0444,
3225 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3227 .mode = 0444,
3231 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3233 .mode = 0444,
3237 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3239 .mode = 0444,
3243 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3245 .mode = 0444,
3249 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3251 .mode = 0444,
3255 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3257 .mode = 0200,
3261 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3263 .mode = 0200,
3267 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3269 .mode = 0200,
3273 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3275 .mode = 0200,
3279 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
3281 .mode = 0644,
3285 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
3288 .mode = 0444,
3301 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
3303 .mode = 0444,
3307 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
3309 .mode = 0444,
3313 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
3315 .mode = 0444,
3320 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
3322 .mode = 0444,
3327 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
3329 .mode = 0444,
3333 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
3335 .mode = 0444,
3339 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3341 .mode = 0444,
3345 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3347 .mode = 0444,
3351 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3353 .mode = 0444,
3357 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3359 .mode = 0444,
3363 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3365 .mode = 0444,
3369 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3371 .mode = 0444,
3375 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3377 .mode = 0444,
3381 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3383 .mode = 0444,
3387 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3389 .mode = 0200,
3393 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3395 .mode = 0200,
3399 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3401 .mode = 0200,
3405 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3407 .mode = 0200,
3411 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
3413 .mode = 0644,
3417 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
3420 .mode = 0444,
3433 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
3435 .mode = 0444,
3439 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
3441 .mode = 0444,
3445 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET,
3447 .mode = 0444,
3451 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET,
3453 .mode = 0444,
3457 .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET,
3459 .mode = 0444,
3463 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
3465 .mode = 0444,
3470 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
3472 .mode = 0444,
3477 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET,
3479 .mode = 0444,
3484 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET,
3486 .mode = 0444,
3491 .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET,
3493 .mode = 0444,
3498 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
3500 .mode = 0444,
3504 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
3506 .mode = 0444,
3510 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET,
3512 .mode = 0444,
3516 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET,
3518 .mode = 0444,
3522 .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET,
3524 .mode = 0444,
3528 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,
3530 .mode = 0200,
3534 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,
3536 .mode = 0200,
3540 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,
3542 .mode = 0644,
3546 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,
3548 .mode = 0644,
3552 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
3554 .mode = 0644,
3559 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
3561 .mode = 0644,
3565 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
3567 .mode = 0644,
3571 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
3573 .mode = 0644,
3578 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
3580 .mode = 0644,
3585 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3587 .mode = 0444,
3591 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3593 .mode = 0444,
3597 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3599 .mode = 0444,
3603 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3605 .mode = 0444,
3609 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3611 .mode = 0444,
3615 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3617 .mode = 0444,
3621 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3623 .mode = 0444,
3627 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3629 .mode = 0444,
3633 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3635 .mode = 0444,
3639 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3641 .mode = 0444,
3645 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3647 .mode = 0444,
3651 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3653 .mode = 0444,
3657 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3659 .mode = 0444,
3663 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3665 .mode = 0444,
3669 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3671 .mode = 0444,
3675 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3677 .mode = 0444,
3681 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3683 .mode = 0444,
3687 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3689 .mode = 0444,
3693 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3695 .mode = 0444,
3699 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3701 .mode = 0200,
3705 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3707 .mode = 0200,
3711 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3713 .mode = 0200,
3717 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3719 .mode = 0200,
3723 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3725 .mode = 0200,
3729 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3731 .mode = 0200,
3735 .reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET,
3738 .mode = 0444,
3742 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
3744 .mode = 0644,
3748 .reg = MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET,
3750 .mode = 0644,
3754 .reg = MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET,
3756 .mode = 0644,
3760 .reg = MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET,
3762 .mode = 0644,
3766 .reg = MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET,
3768 .mode = 0644,
3772 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
3775 .mode = 0444,
3779 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET,
3782 .mode = 0444,
3786 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION,
3788 .mode = 0444,
3792 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3794 .mode = 0444,
3798 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3800 .mode = 0444,
3804 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3806 .mode = 0444,
3810 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3812 .mode = 0444,
3816 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET,
3819 .mode = 0444,
3823 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
3825 .mode = 0644,
3830 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
3832 .mode = 0644,
3836 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
3838 .mode = 0644,
3842 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3844 .mode = 0444,
3848 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3850 .mode = 0444,
3854 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3856 .mode = 0444,
3860 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3862 .mode = 0444,
3866 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3868 .mode = 0444,
3872 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3874 .mode = 0444,
3878 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3880 .mode = 0444,
3884 .reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT,
3887 .mode = 0644,
3891 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET,
3893 .mode = 0444,
3897 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET,
3899 .mode = 0444,
3903 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET,
3905 .mode = 0444,
3909 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET,
3911 .mode = 0444,
3924 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
3926 .mode = 0444,
3930 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
3932 .mode = 0444,
3936 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET,
3938 .mode = 0444,
3942 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET,
3944 .mode = 0444,
3948 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
3950 .mode = 0444,
3955 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
3957 .mode = 0444,
3962 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET,
3964 .mode = 0444,
3969 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET,
3971 .mode = 0444,
3976 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
3978 .mode = 0444,
3982 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
3984 .mode = 0444,
3988 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET,
3990 .mode = 0444,
3994 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET,
3996 .mode = 0444,
4000 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
4002 .mode = 0644,
4006 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
4008 .mode = 0644,
4012 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
4014 .mode = 0644,
4018 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
4020 .mode = 0644,
4024 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
4026 .mode = 0644,
4030 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
4032 .mode = 0644,
4036 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
4038 .mode = 0644,
4042 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
4044 .mode = 0644,
4048 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4050 .mode = 0444,
4054 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4056 .mode = 0444,
4060 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4062 .mode = 0444,
4066 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4068 .mode = 0444,
4072 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4074 .mode = 0444,
4078 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4080 .mode = 0444,
4084 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4086 .mode = 0444,
4090 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4092 .mode = 0444,
4096 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4098 .mode = 0444,
4102 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4104 .mode = 0444,
4108 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4110 .mode = 0444,
4114 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4116 .mode = 0444,
4120 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4122 .mode = 0444,
4126 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4128 .mode = 0444,
4132 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4134 .mode = 0444,
4138 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4140 .mode = 0444,
4144 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4146 .mode = 0444,
4150 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4152 .mode = 0444,
4156 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4158 .mode = 0444,
4162 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4164 .mode = 0444,
4168 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4170 .mode = 0444,
4174 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET,
4177 .mode = 0444,
4181 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
4183 .mode = 0644,
4187 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
4189 .mode = 0644,
4193 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
4195 .mode = 0644,
4199 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
4201 .mode = 0200,
4205 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
4207 .mode = 0200,
4211 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
4213 .mode = 0200,
4217 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
4219 .mode = 0200,
4223 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
4225 .mode = 0200,
4229 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
4231 .mode = 0200,
4235 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
4237 .mode = 0200,
4241 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
4243 .mode = 0200,
4247 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4249 .mode = 0200,
4253 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4255 .mode = 0200,
4259 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4261 .mode = 0200,
4265 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4267 .mode = 0200,
4271 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4273 .mode = 0200,
4277 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4279 .mode = 0200,
4283 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4285 .mode = 0644,
4289 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4291 .mode = 0644,
4295 .reg = MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE,
4298 .mode = 0644,
4302 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET,
4304 .mode = 0644,
4308 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET,
4310 .mode = 0644,
4314 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
4317 .mode = 0444,
4321 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION,
4323 .mode = 0444,
4327 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
4329 .mode = 0644,
4333 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
4335 .mode = 0644,
4339 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
4341 .mode = 0644,
4345 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
4347 .mode = 0644,
4351 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
4353 .mode = 0644,
4357 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
4359 .mode = 0644,
4363 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
4365 .mode = 0644,
4369 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
4371 .mode = 0644,
4375 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET,
4377 .mode = 0444,
4381 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET,
4383 .mode = 0444,
4387 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET,
4389 .mode = 0444,
4393 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET,
4395 .mode = 0444,
4408 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
4410 .mode = 0444,
4414 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
4416 .mode = 0444,
4421 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
4423 .mode = 0444,
4427 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4429 .mode = 0444,
4433 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4435 .mode = 0444,
4439 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4441 .mode = 0444,
4445 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4447 .mode = 0444,
4451 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4453 .mode = 0444,
4457 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4459 .mode = 0444,
4463 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4465 .mode = 0444,
4469 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4471 .mode = 0444,
4475 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4477 .mode = 0444,
4481 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4483 .mode = 0444,
4487 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4489 .mode = 0444,
4493 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4495 .mode = 0444,
4499 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4501 .mode = 0444,
4505 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4507 .mode = 0200,
4511 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4513 .mode = 0200,
4517 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
4519 .mode = 0644,
4523 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
4525 .mode = 0644,
4529 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
4531 .mode = 0200,
4535 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4537 .mode = 0444,
4541 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4543 .mode = 0444,
4547 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4549 .mode = 0444,
4553 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4555 .mode = 0444,
4559 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET,
4562 .mode = 0444,
4566 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
4568 .mode = 0644,
4572 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
4574 .mode = 0644,
4578 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET,
4580 .mode = 0444,
4584 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET,
4586 .mode = 0444,
4590 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET,
4592 .mode = 0444,
4596 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET,
4598 .mode = 0444,
4602 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET,
4604 .mode = 0444,
4617 .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET,
4621 .reg = MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET,
4625 .reg = MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET,
4629 .reg = MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET,
4633 .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET,
4642 .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET,
4650 .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET,
4658 .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET,
4666 .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET,
4674 .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET,
4682 .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET,
4690 .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET,
4698 .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET,
4706 .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET,
4714 .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET,
4722 .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET,
4730 .reg = MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET,
4737 .reg = MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET,
4760 .reg = MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET,
4766 .reg = MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET,
4772 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET,
4778 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4787 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
4793 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
4799 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET,
4810 .identity = "mlx-wdt-main",
4816 .identity = "mlx-wdt-aux",
4826 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
4832 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
4838 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET,
4843 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
4849 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4858 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
4864 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
4870 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET,
4875 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
4886 .identity = "mlx-wdt-main",
4892 .identity = "mlx-wdt-aux",
4904 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
4910 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
4916 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
4921 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
4927 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4936 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
4942 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
4948 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
4953 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
4964 .identity = "mlx-wdt-main",
4970 .identity = "mlx-wdt-aux",
4974 static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) in mlxplat_mlxcpld_writeable_reg() argument
4976 switch (reg) { in mlxplat_mlxcpld_writeable_reg()
5068 static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) in mlxplat_mlxcpld_readable_reg() argument
5070 switch (reg) { in mlxplat_mlxcpld_readable_reg()
5233 static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) in mlxplat_mlxcpld_volatile_reg() argument
5235 switch (reg) { in mlxplat_mlxcpld_volatile_reg()
5442 mlxplat_mlxcpld_reg_read(void *context, unsigned int reg, unsigned int *val) in mlxplat_mlxcpld_reg_read() argument
5446 *val = ioread8(ctx->base + reg); in mlxplat_mlxcpld_reg_read()
5451 mlxplat_mlxcpld_reg_write(void *context, unsigned int reg, unsigned int val) in mlxplat_mlxcpld_reg_write() argument
5455 iowrite8(val, ctx->base + reg); in mlxplat_mlxcpld_reg_write()
5544 [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"),
5566 ret = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, ®val); in mlxplat_reboot_notifier()
5569 regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, in mlxplat_reboot_notifier()
5586 regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, MLXPLAT_CPLD_HALT_MASK); in mlxplat_poweroff()
5592 mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, -1, in mlxplat_register_platform_device()
5614 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_default_matched()
5615 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_default_matched()
5637 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_default_wc_matched()
5638 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_default_wc_matched()
5660 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_default_eth_wc_blade_matched()
5661 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_default_eth_wc_blade_matched()
5685 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_msn21xx_matched()
5686 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_msn21xx_matched()
5708 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_msn274x_matched()
5709 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_msn274x_matched()
5731 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_msn201x_matched()
5732 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_msn201x_matched()
5754 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_qmb7xx_matched()
5755 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_qmb7xx_matched()
5780 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; in mlxplat_dmi_comex_matched()
5805 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_ng400_matched()
5806 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_ng400_matched()
5826 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR; in mlxplat_dmi_modular_matched()
5846 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_chassis_blade_matched()
5847 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_chassis_blade_matched()
5868 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_rack_switch_matched()
5869 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_rack_switch_matched()
5889 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_ng800_matched()
5890 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_ng800_matched()
5910 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_l1_switch_matched()
5911 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_l1_switch_matched()
6124 return -ENODEV; in mlxplat_mlxcpld_verify_bus_topology()
6129 shift = *nr - mlxplat_mux_data[i].parent; in mlxplat_mlxcpld_verify_bus_topology()
6135 mlxplat_hotplug->shift_nr = shift; in mlxplat_mlxcpld_verify_bus_topology()
6166 mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev, in mlxplat_lpc_cpld_device_init()
6169 err = -ENOMEM; in mlxplat_lpc_cpld_device_init()
6196 return -ENODEV; in mlxplat_pci_fpga_device_init()
6200 dev_err(&pci_dev->dev, "pci_enable_device failed with error %d\n", err); in mlxplat_pci_fpga_device_init()
6206 dev_err(&pci_dev->dev, "pci_request_regions failed with error %d\n", err); in mlxplat_pci_fpga_device_init()
6210 err = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(64)); in mlxplat_pci_fpga_device_init()
6212 err = dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32)); in mlxplat_pci_fpga_device_init()
6214 dev_err(&pci_dev->dev, "dma_set_mask failed with error %d\n", err); in mlxplat_pci_fpga_device_init()
6221 pci_mem_addr = devm_ioremap(&pci_dev->dev, pci_resource_start(pci_dev, 0), in mlxplat_pci_fpga_device_init()
6224 dev_err(&mlxplat_dev->dev, "ioremap failed\n"); in mlxplat_pci_fpga_device_init()
6225 err = -EIO; in mlxplat_pci_fpga_device_init()
6299 if (err == -ENODEV) in mlxplat_logicdev_init()
6319 mlxplat_hotplug->regmap = priv->regmap; in mlxplat_platdevs_init()
6320 if (priv->irq_fpga) in mlxplat_platdevs_init()
6321 mlxplat_hotplug->irq = priv->irq_fpga; in mlxplat_platdevs_init()
6322 priv->pdev_hotplug = in mlxplat_platdevs_init()
6323 platform_device_register_resndata(&mlxplat_dev->dev, in mlxplat_platdevs_init()
6324 "mlxreg-hotplug", PLATFORM_DEVID_NONE, in mlxplat_platdevs_init()
6325 priv->hotplug_resources, in mlxplat_platdevs_init()
6326 priv->hotplug_resources_size, in mlxplat_platdevs_init()
6328 if (IS_ERR(priv->pdev_hotplug)) { in mlxplat_platdevs_init()
6329 err = PTR_ERR(priv->pdev_hotplug); in mlxplat_platdevs_init()
6336 mlxplat_led->regmap = priv->regmap; in mlxplat_platdevs_init()
6337 priv->pdev_led = in mlxplat_platdevs_init()
6338 platform_device_register_resndata(&mlxplat_dev->dev, "leds-mlxreg", in mlxplat_platdevs_init()
6341 if (IS_ERR(priv->pdev_led)) { in mlxplat_platdevs_init()
6342 err = PTR_ERR(priv->pdev_led); in mlxplat_platdevs_init()
6349 mlxplat_regs_io->regmap = priv->regmap; in mlxplat_platdevs_init()
6350 priv->pdev_io_regs = platform_device_register_resndata(&mlxplat_dev->dev, in mlxplat_platdevs_init()
6351 "mlxreg-io", in mlxplat_platdevs_init()
6355 if (IS_ERR(priv->pdev_io_regs)) { in mlxplat_platdevs_init()
6356 err = PTR_ERR(priv->pdev_io_regs); in mlxplat_platdevs_init()
6363 mlxplat_fan->regmap = priv->regmap; in mlxplat_platdevs_init()
6364 priv->pdev_fan = platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-fan", in mlxplat_platdevs_init()
6368 if (IS_ERR(priv->pdev_fan)) { in mlxplat_platdevs_init()
6369 err = PTR_ERR(priv->pdev_fan); in mlxplat_platdevs_init()
6375 err = mlxplat_mlxcpld_check_wd_capability(priv->regmap); in mlxplat_platdevs_init()
6380 mlxplat_wd_data[i]->regmap = priv->regmap; in mlxplat_platdevs_init()
6381 priv->pdev_wd[i] = in mlxplat_platdevs_init()
6382 platform_device_register_resndata(&mlxplat_dev->dev, "mlx-wdt", i, in mlxplat_platdevs_init()
6385 if (IS_ERR(priv->pdev_wd[i])) { in mlxplat_platdevs_init()
6386 err = PTR_ERR(priv->pdev_wd[i]); in mlxplat_platdevs_init()
6395 while (--i >= 0) in mlxplat_platdevs_init()
6396 platform_device_unregister(priv->pdev_wd[i]); in mlxplat_platdevs_init()
6399 platform_device_unregister(priv->pdev_io_regs); in mlxplat_platdevs_init()
6402 platform_device_unregister(priv->pdev_led); in mlxplat_platdevs_init()
6405 platform_device_unregister(priv->pdev_hotplug); in mlxplat_platdevs_init()
6414 for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--) in mlxplat_platdevs_exit()
6415 platform_device_unregister(priv->pdev_wd[i]); in mlxplat_platdevs_exit()
6416 if (priv->pdev_fan) in mlxplat_platdevs_exit()
6417 platform_device_unregister(priv->pdev_fan); in mlxplat_platdevs_exit()
6418 if (priv->pdev_io_regs) in mlxplat_platdevs_exit()
6419 platform_device_unregister(priv->pdev_io_regs); in mlxplat_platdevs_exit()
6420 if (priv->pdev_led) in mlxplat_platdevs_exit()
6421 platform_device_unregister(priv->pdev_led); in mlxplat_platdevs_exit()
6422 if (priv->pdev_hotplug) in mlxplat_platdevs_exit()
6423 platform_device_unregister(priv->pdev_hotplug); in mlxplat_platdevs_exit()
6439 if (!priv->pdev_i2c) { in mlxplat_i2c_mux_topology_init()
6440 priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_NOTIFIED; in mlxplat_i2c_mux_topology_init()
6444 priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED; in mlxplat_i2c_mux_topology_init()
6446 priv->pdev_mux[i] = platform_device_register_resndata(&priv->pdev_i2c->dev, in mlxplat_i2c_mux_topology_init()
6447 "i2c-mux-reg", i, NULL, 0, in mlxplat_i2c_mux_topology_init()
6450 if (IS_ERR(priv->pdev_mux[i])) { in mlxplat_i2c_mux_topology_init()
6451 err = PTR_ERR(priv->pdev_mux[i]); in mlxplat_i2c_mux_topology_init()
6459 while (--i >= 0) in mlxplat_i2c_mux_topology_init()
6460 platform_device_unregister(priv->pdev_mux[i]); in mlxplat_i2c_mux_topology_init()
6468 for (i = mlxplat_mux_num - 1; i >= 0 ; i--) { in mlxplat_i2c_mux_topology_exit()
6469 if (priv->pdev_mux[i]) in mlxplat_i2c_mux_topology_exit()
6470 platform_device_unregister(priv->pdev_mux[i]); in mlxplat_i2c_mux_topology_exit()
6492 nr = (nr == mlxplat_max_adap_num) ? -1 : nr; in mlxplat_i2c_main_init()
6493 mlxplat_i2c->regmap = priv->regmap; in mlxplat_i2c_main_init()
6494 mlxplat_i2c->handle = priv; in mlxplat_i2c_main_init()
6496 /* Set mapped base address of I2C-LPC bridge over PCIe */ in mlxplat_i2c_main_init()
6498 mlxplat_i2c->addr = i2c_bridge_addr; in mlxplat_i2c_main_init()
6499 priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld", in mlxplat_i2c_main_init()
6500 nr, priv->hotplug_resources, in mlxplat_i2c_main_init()
6501 priv->hotplug_resources_size, in mlxplat_i2c_main_init()
6503 if (IS_ERR(priv->pdev_i2c)) { in mlxplat_i2c_main_init()
6504 err = PTR_ERR(priv->pdev_i2c); in mlxplat_i2c_main_init()
6508 if (priv->i2c_main_init_status == MLXPLAT_I2C_MAIN_BUS_NOTIFIED) { in mlxplat_i2c_main_init()
6517 platform_device_unregister(priv->pdev_i2c); in mlxplat_i2c_main_init()
6527 if (priv->pdev_i2c) in mlxplat_i2c_main_exit()
6528 platform_device_unregister(priv->pdev_i2c); in mlxplat_i2c_main_exit()
6539 acpi_dev = ACPI_COMPANION(&pdev->dev); in mlxplat_probe()
6543 return -ENODEV; in mlxplat_probe()
6551 priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv), in mlxplat_probe()
6554 err = -ENOMEM; in mlxplat_probe()
6558 priv->hotplug_resources = hotplug_resources; in mlxplat_probe()
6559 priv->hotplug_resources_size = hotplug_resources_size; in mlxplat_probe()
6560 priv->irq_fpga = irq_fpga; in mlxplat_probe()
6565 priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL, in mlxplat_probe()
6568 if (IS_ERR(priv->regmap)) { in mlxplat_probe()
6569 err = PTR_ERR(priv->regmap); in mlxplat_probe()
6574 for (i = 0; i < mlxplat_regmap_config->num_reg_defaults; i++) { in mlxplat_probe()
6575 err = regmap_write(priv->regmap, in mlxplat_probe()
6576 mlxplat_regmap_config->reg_defaults[i].reg, in mlxplat_probe()
6577 mlxplat_regmap_config->reg_defaults[i].def); in mlxplat_probe()
6587 regcache_mark_dirty(priv->regmap); in mlxplat_probe()
6588 err = regcache_sync(priv->regmap); in mlxplat_probe()
6644 return -ENODEV; in mlxplat_init()