Lines Matching full:bit
63 {"AON2_OFF_STS", BIT(0)},
64 {"AON3_OFF_STS", BIT(1)},
65 {"AON4_OFF_STS", BIT(2)},
66 {"AON5_OFF_STS", BIT(3)},
67 {"AON1_OFF_STS", BIT(4)},
68 {"XTAL_LVM_OFF_STS", BIT(5)},
69 {"AON3_SPL_OFF_STS", BIT(9)},
70 {"DMI3FPW_0_PLL_OFF_STS", BIT(10)},
71 {"DMI3FPW_1_PLL_OFF_STS", BIT(11)},
72 {"G5X16FPW_0_PLL_OFF_STS", BIT(14)},
73 {"G5X16FPW_1_PLL_OFF_STS", BIT(15)},
74 {"G5X16FPW_2_PLL_OFF_STS", BIT(16)},
75 {"XTAL_AGGR_OFF_STS", BIT(17)},
76 {"USB2_PLL_OFF_STS", BIT(18)},
77 {"G5X16FPW_3_PLL_OFF_STS", BIT(19)},
78 {"BCLK_EXT_INJ_CLK_OFF_STS", BIT(20)},
79 {"PHY_OC_EXT_INJ_CLK_OFF_STS", BIT(21)},
80 {"FILTER_PLL_OFF_STS", BIT(22)},
81 {"FABRIC_PLL_OFF_STS", BIT(25)},
82 {"SOC_PLL_OFF_STS", BIT(26)},
83 {"PCIEFAB_PLL_OFF_STS", BIT(27)},
84 {"REF_PLL_OFF_STS", BIT(28)},
85 {"GENLOCK_FILTER_PLL_OFF_STS", BIT(30)},
86 {"RTC_PLL_OFF_STS", BIT(31)},
91 {"PMC_PGD0_PG_STS", BIT(0)},
92 {"DMI_PGD0_PG_STS", BIT(1)},
93 {"ESPISPI_PGD0_PG_STS", BIT(2)},
94 {"XHCI_PGD0_PG_STS", BIT(3)},
95 {"SPA_PGD0_PG_STS", BIT(4)},
96 {"SPB_PGD0_PG_STS", BIT(5)},
97 {"SPC_PGD0_PG_STS", BIT(6)},
98 {"GBE_PGD0_PG_STS", BIT(7)},
99 {"SATA_PGD0_PG_STS", BIT(8)},
100 {"FIACPCB_P5x16_PGD0_PG_STS", BIT(9)},
101 {"G5x16FPW_PGD0_PG_STS", BIT(10)},
102 {"FIA_D_PGD0_PG_STS", BIT(11)},
103 {"MPFPW2_PGD0_PG_STS", BIT(12)},
104 {"SPD_PGD0_PG_STS", BIT(13)},
105 {"LPSS_PGD0_PG_STS", BIT(14)},
106 {"LPC_PGD0_PG_STS", BIT(15)},
107 {"SMB_PGD0_PG_STS", BIT(16)},
108 {"ISH_PGD0_PG_STS", BIT(17)},
109 {"P2S_PGD0_PG_STS", BIT(18)},
110 {"NPK_PGD0_PG_STS", BIT(19)},
111 {"DMI3FPW_PGD0_PG_STS", BIT(20)},
112 {"GBETSN1_PGD0_PG_STS", BIT(21)},
113 {"FUSE_PGD0_PG_STS", BIT(22)},
114 {"FIACPCB_D_PGD0_PG_STS", BIT(23)},
115 {"FUSEGPSB_PGD0_PG_STS", BIT(24)},
116 {"XDCI_PGD0_PG_STS", BIT(25)},
117 {"EXI_PGD0_PG_STS", BIT(26)},
118 {"CSE_PGD0_PG_STS", BIT(27)},
119 {"KVMCC_PGD0_PG_STS", BIT(28)},
120 {"PMT_PGD0_PG_STS", BIT(29)},
121 {"CLINK_PGD0_PG_STS", BIT(30)},
122 {"PTIO_PGD0_PG_STS", BIT(31)},
127 {"USBR0_PGD0_PG_STS", BIT(0)},
128 {"SUSRAM_PGD0_PG_STS", BIT(1)},
129 {"SMT1_PGD0_PG_STS", BIT(2)},
130 {"FIACPCB_U_PGD0_PG_STS", BIT(3)},
131 {"SMS2_PGD0_PG_STS", BIT(4)},
132 {"SMS1_PGD0_PG_STS", BIT(5)},
133 {"CSMERTC_PGD0_PG_STS", BIT(6)},
134 {"CSMEPSF_PGD0_PG_STS", BIT(7)},
135 {"SBR0_PGD0_PG_STS", BIT(8)},
136 {"SBR1_PGD0_PG_STS", BIT(9)},
137 {"SBR2_PGD0_PG_STS", BIT(10)},
138 {"SBR3_PGD0_PG_STS", BIT(11)},
139 {"MPFPW1_PGD0_PG_STS", BIT(12)},
140 {"SBR5_PGD0_PG_STS", BIT(13)},
141 {"FIA_X_PGD0_PG_STS", BIT(14)},
142 {"FIACPCB_X_PGD0_PG_STS", BIT(15)},
143 {"SBRG_PGD0_PG_STS", BIT(16)},
144 {"SOC_D2D_PGD1_PG_STS", BIT(17)},
145 {"PSF4_PGD0_PG_STS", BIT(18)},
146 {"CNVI_PGD0_PG_STS", BIT(19)},
147 {"UFSX2_PGD0_PG_STS", BIT(20)},
148 {"ENDBG_PGD0_PG_STS", BIT(21)},
149 {"DBG_PSF_PGD0_PG_STS", BIT(22)},
150 {"SBR6_PGD0_PG_STS", BIT(23)},
151 {"SOC_D2D_PGD2_PG_STS", BIT(24)},
152 {"NPK_PGD1_PG_STS", BIT(25)},
153 {"DMI3_PGD0_PG_STS", BIT(26)},
154 {"DBG_SBR_PGD0_PG_STS", BIT(27)},
155 {"SOC_D2D_PGD0_PG_STS", BIT(28)},
156 {"PSF6_PGD0_PG_STS", BIT(29)},
157 {"PSF7_PGD0_PG_STS", BIT(30)},
158 {"MPFPW3_PGD0_PG_STS", BIT(31)},
163 {"PSF8_PGD0_PG_STS", BIT(0)},
164 {"FIA_PGD0_PG_STS", BIT(1)},
165 {"SOC_D2D_PGD3_PG_STS", BIT(2)},
166 {"FIA_U_PGD0_PG_STS", BIT(3)},
167 {"TAM_PGD0_PG_STS", BIT(4)},
168 {"GBETSN_PGD0_PG_STS", BIT(5)},
169 {"TBTLSX_PGD0_PG_STS", BIT(6)},
170 {"THC0_PGD0_PG_STS", BIT(7)},
171 {"THC1_PGD0_PG_STS", BIT(8)},
172 {"PMC_PGD1_PG_STS", BIT(9)},
173 {"FIA_P5x16_PGD0_PG_STS", BIT(10)},
174 {"GNA_PGD0_PG_STS", BIT(11)},
175 {"ACE_PGD0_PG_STS", BIT(12)},
176 {"ACE_PGD1_PG_STS", BIT(13)},
177 {"ACE_PGD2_PG_STS", BIT(14)},
178 {"ACE_PGD3_PG_STS", BIT(15)},
179 {"ACE_PGD4_PG_STS", BIT(16)},
180 {"ACE_PGD5_PG_STS", BIT(17)},
181 {"ACE_PGD6_PG_STS", BIT(18)},
182 {"ACE_PGD7_PG_STS", BIT(19)},
183 {"ACE_PGD8_PG_STS", BIT(20)},
184 {"FIA_PGS_PGD0_PG_STS", BIT(21)},
185 {"FIACPCB_PGS_PGD0_PG_STS", BIT(22)},
186 {"FUSEPMSB_PGD0_PG_STS", BIT(23)},
191 {"CSMERTC_D3_STS", BIT(1)},
192 {"SUSRAM_D3_STS", BIT(2)},
193 {"CSE_D3_STS", BIT(4)},
194 {"KVMCC_D3_STS", BIT(5)},
195 {"USBR0_D3_STS", BIT(6)},
196 {"ISH_D3_STS", BIT(7)},
197 {"SMT1_D3_STS", BIT(8)},
198 {"SMT2_D3_STS", BIT(9)},
199 {"SMT3_D3_STS", BIT(10)},
200 {"GNA_D3_STS", BIT(12)},
201 {"CLINK_D3_STS", BIT(14)},
202 {"PTIO_D3_STS", BIT(16)},
203 {"PMT_D3_STS", BIT(17)},
204 {"SMS1_D3_STS", BIT(18)},
205 {"SMS2_D3_STS", BIT(19)},
210 {"GBETSN_D3_STS", BIT(13)},
211 {"THC0_D3_STS", BIT(14)},
212 {"THC1_D3_STS", BIT(15)},
213 {"ACE_D3_STS", BIT(23)},
218 {"DTS0_VNN_REQ_STS", BIT(7)},
219 {"GPIOCOM5_VNN_REQ_STS", BIT(11)},
242 {"RSVD64", BIT(0)},
243 {"RSVD65", BIT(1)},
244 {"RSVD66", BIT(2)},
245 {"RSVD67", BIT(3)},
246 {"RSVD68", BIT(4)},
247 {"GBETSN", BIT(5)},
248 {"TBTLSX", BIT(6)},
327 {"AON2_OFF_STS", BIT(0)},
328 {"AON3_OFF_STS", BIT(1)},
329 {"AON4_OFF_STS", BIT(2)},
330 {"AON2_SPL_OFF_STS", BIT(3)},
331 {"AONL_OFF_STS", BIT(4)},
332 {"XTAL_LVM_OFF_STS", BIT(5)},
333 {"AON5_ACRO_OFF_STS", BIT(6)},
334 {"AON6_ACRO_OFF_STS", BIT(7)},
335 {"USB3_PLL_OFF_STS", BIT(8)},
336 {"ACRO_OFF_STS", BIT(9)},
337 {"AUDIO_PLL_OFF_STS", BIT(10)},
338 {"MAIN_CRO_OFF_STS", BIT(11)},
339 {"MAIN_DIVIDER_OFF_STS", BIT(12)},
340 {"REF_PLL_NON_OC_OFF_STS", BIT(13)},
341 {"DMI_PLL_OFF_STS", BIT(14)},
342 {"PHY_EXT_INJ_OFF_STS", BIT(15)},
343 {"AON6_MCRO_OFF_STS", BIT(16)},
344 {"XTAL_AGGR_OFF_STS", BIT(17)},
345 {"USB2_PLL_OFF_STS", BIT(18)},
346 {"TSN0_PLL_OFF_STS", BIT(19)},
347 {"TSN1_PLL_OFF_STS", BIT(20)},
348 {"GBE_PLL_OFF_STS", BIT(21)},
349 {"SATA_PLL_OFF_STS", BIT(22)},
350 {"PCIE0_PLL_OFF_STS", BIT(23)},
351 {"PCIE1_PLL_OFF_STS", BIT(24)},
352 {"PCIE2_PLL_OFF_STS", BIT(26)},
353 {"PCIE3_PLL_OFF_STS", BIT(27)},
354 {"REF_PLL_OFF_STS", BIT(28)},
355 {"PCIE4_PLL_OFF_STS", BIT(29)},
356 {"PCIE5_PLL_OFF_STS", BIT(30)},
357 {"REF38P4_PLL_OFF_STS", BIT(31)},
362 {"PMC_PGD0_PG_STS", BIT(0)},
363 {"DMI_PGD0_PG_STS", BIT(1)},
364 {"ESPISPI_PGD0_PG_STS", BIT(2)},
365 {"XHCI_PGD0_PG_STS", BIT(3)},
366 {"SPA_PGD0_PG_STS", BIT(4)},
367 {"SPB_PGD0_PG_STS", BIT(5)},
368 {"SPC_PGD0_PG_STS", BIT(6)},
369 {"GBE_PGD0_PG_STS", BIT(7)},
370 {"SATA_PGD0_PG_STS", BIT(8)},
371 {"FIA_X_PGD0_PG_STS", BIT(9)},
372 {"MPFPW4_PGD0_PG_STS", BIT(10)},
373 {"EAH_PGD0_PG_STS", BIT(11)},
374 {"MPFPW1_PGD0_PG_STS", BIT(12)},
375 {"SPD_PGD0_PG_STS", BIT(13)},
376 {"LPSS_PGD0_PG_STS", BIT(14)},
377 {"LPC_PGD0_PG_STS", BIT(15)},
378 {"SMB_PGD0_PG_STS", BIT(16)},
379 {"ISH_PGD0_PG_STS", BIT(17)},
380 {"P2S_PGD0_PG_STS", BIT(18)},
381 {"NPK_PGD0_PG_STS", BIT(19)},
382 {"U3FPW1_PGD0_PG_STS", BIT(20)},
383 {"PECI_PGD0_PG_STS", BIT(21)},
384 {"FUSE_PGD0_PG_STS", BIT(22)},
385 {"SBR8_PGD0_PG_STS", BIT(23)},
386 {"EXE_PGD0_PG_STS", BIT(24)},
387 {"XDCI_PGD0_PG_STS", BIT(25)},
388 {"EXI_PGD0_PG_STS", BIT(26)},
389 {"CSE_PGD0_PG_STS", BIT(27)},
390 {"KVMCC_PGD0_PG_STS", BIT(28)},
391 {"PMT_PGD0_PG_STS", BIT(29)},
392 {"CLINK_PGD0_PG_STS", BIT(30)},
393 {"PTIO_PGD0_PG_STS", BIT(31)},
398 {"USBR0_PGD0_PG_STS", BIT(0)},
399 {"SUSRAM_PGD0_PG_STS", BIT(1)},
400 {"SMT1_PGD0_PG_STS", BIT(2)},
401 {"SMT4_PGD0_PG_STS", BIT(3)},
402 {"SMS2_PGD0_PG_STS", BIT(4)},
403 {"SMS1_PGD0_PG_STS", BIT(5)},
404 {"CSMERTC_PGD0_PG_STS", BIT(6)},
405 {"CSMEPSF_PGD0_PG_STS", BIT(7)},
406 {"SBR0_PGD0_PG_STS", BIT(8)},
407 {"SBR1_PGD0_PG_STS", BIT(9)},
408 {"SBR2_PGD0_PG_STS", BIT(10)},
409 {"SBR3_PGD0_PG_STS", BIT(11)},
410 {"SBR4_PGD0_PG_STS", BIT(12)},
411 {"SBR5_PGD0_PG_STS", BIT(13)},
412 {"MPFPW3_PGD0_PG_STS", BIT(14)},
413 {"PSF1_PGD0_PG_STS", BIT(15)},
414 {"PSF2_PGD0_PG_STS", BIT(16)},
415 {"PSF3_PGD0_PG_STS", BIT(17)},
416 {"PSF4_PGD0_PG_STS", BIT(18)},
417 {"CNVI_PGD0_PG_STS", BIT(19)},
418 {"DMI3_PGD0_PG_STS", BIT(20)},
419 {"ENDBG_PGD0_PG_STS", BIT(21)},
420 {"DBG_SBR_PGD0_PG_STS", BIT(22)},
421 {"SBR6_PGD0_PG_STS", BIT(23)},
422 {"SBR7_PGD0_PG_STS", BIT(24)},
423 {"NPK_PGD1_PG_STS", BIT(25)},
424 {"U3FPW3_PGD0_PG_STS", BIT(26)},
425 {"MPFPW2_PGD0_PG_STS", BIT(27)},
426 {"MPFPW7_PGD0_PG_STS", BIT(28)},
427 {"GBETSN1_PGD0_PG_STS", BIT(29)},
428 {"PSF7_PGD0_PG_STS", BIT(30)},
429 {"FIA2_PGD0_PG_STS", BIT(31)},
434 {"U3FPW2_PGD0_PG_STS", BIT(0)},
435 {"FIA_PGD0_PG_STS", BIT(1)},
436 {"FIACPCB_X_PGD0_PG_STS", BIT(2)},
437 {"FIA1_PGD0_PG_STS", BIT(3)},
438 {"TAM_PGD0_PG_STS", BIT(4)},
439 {"GBETSN_PGD0_PG_STS", BIT(5)},
440 {"SBR9_PGD0_PG_STS", BIT(6)},
441 {"THC0_PGD0_PG_STS", BIT(7)},
442 {"THC1_PGD0_PG_STS", BIT(8)},
443 {"PMC_PGD1_PG_STS", BIT(9)},
444 {"DBC_PGD0_PG_STS", BIT(10)},
445 {"DBG_PSF_PGD0_PG_STS", BIT(11)},
446 {"SPF_PGD0_PG_STS", BIT(12)},
447 {"ACE_PGD0_PG_STS", BIT(13)},
448 {"ACE_PGD1_PG_STS", BIT(14)},
449 {"ACE_PGD2_PG_STS", BIT(15)},
450 {"ACE_PGD3_PG_STS", BIT(16)},
451 {"ACE_PGD4_PG_STS", BIT(17)},
452 {"ACE_PGD5_PG_STS", BIT(18)},
453 {"ACE_PGD6_PG_STS", BIT(19)},
454 {"ACE_PGD7_PG_STS", BIT(20)},
455 {"SPE_PGD0_PG_STS", BIT(21)},
456 {"MPFPW5_PG_STS", BIT(22)},
461 {"SPF_D3_STS", BIT(0)},
462 {"LPSS_D3_STS", BIT(3)},
463 {"XDCI_D3_STS", BIT(4)},
464 {"XHCI_D3_STS", BIT(5)},
465 {"SPA_D3_STS", BIT(12)},
466 {"SPB_D3_STS", BIT(13)},
467 {"SPC_D3_STS", BIT(14)},
468 {"SPD_D3_STS", BIT(15)},
469 {"SPE_D3_STS", BIT(16)},
470 {"ESPISPI_D3_STS", BIT(18)},
471 {"SATA_D3_STS", BIT(20)},
472 {"PSTH_D3_STS", BIT(21)},
473 {"DMI_D3_STS", BIT(22)},
478 {"GBETSN1_D3_STS", BIT(14)},
479 {"GBE_D3_STS", BIT(19)},
480 {"ITSS_D3_STS", BIT(23)},
481 {"P2S_D3_STS", BIT(24)},
482 {"CNVI_D3_STS", BIT(27)},
487 {"CSMERTC_D3_STS", BIT(1)},
488 {"SUSRAM_D3_STS", BIT(2)},
489 {"CSE_D3_STS", BIT(4)},
490 {"KVMCC_D3_STS", BIT(5)},
491 {"USBR0_D3_STS", BIT(6)},
492 {"ISH_D3_STS", BIT(7)},
493 {"SMT1_D3_STS", BIT(8)},
494 {"SMT2_D3_STS", BIT(9)},
495 {"SMT3_D3_STS", BIT(10)},
496 {"SMT4_D3_STS", BIT(11)},
497 {"SMT5_D3_STS", BIT(12)},
498 {"SMT6_D3_STS", BIT(13)},
499 {"CLINK_D3_STS", BIT(14)},
500 {"PTIO_D3_STS", BIT(16)},
501 {"PMT_D3_STS", BIT(17)},
502 {"SMS1_D3_STS", BIT(18)},
503 {"SMS2_D3_STS", BIT(19)},
508 {"ESE_D3_STS", BIT(3)},
509 {"GBETSN_D3_STS", BIT(13)},
510 {"THC0_D3_STS", BIT(14)},
511 {"THC1_D3_STS", BIT(15)},
512 {"ACE_D3_STS", BIT(23)},
517 {"FIA_VNN_REQ_STS", BIT(17)},
518 {"ESPISPI_VNN_REQ_STS", BIT(18)},
523 {"NPK_VNN_REQ_STS", BIT(4)},
524 {"DFXAGG_VNN_REQ_STS", BIT(8)},
525 {"EXI_VNN_REQ_STS", BIT(9)},
526 {"GBE_VNN_REQ_STS", BIT(19)},
527 {"SMB_VNN_REQ_STS", BIT(25)},
528 {"LPC_VNN_REQ_STS", BIT(26)},
529 {"CNVI_VNN_REQ_STS", BIT(27)},
534 {"FIA2_VNN_REQ_STS", BIT(0)},
535 {"CSMERTC_VNN_REQ_STS", BIT(1)},
536 {"CSE_VNN_REQ_STS", BIT(4)},
537 {"ISH_VNN_REQ_STS", BIT(7)},
538 {"SMT1_VNN_REQ_STS", BIT(8)},
539 {"SMT4_VNN_REQ_STS", BIT(11)},
540 {"CLINK_VNN_REQ_STS", BIT(14)},
541 {"SMS1_VNN_REQ_STS", BIT(18)},
542 {"SMS2_VNN_REQ_STS", BIT(19)},
543 {"GPIOCOM4_VNN_REQ_STS", BIT(20)},
544 {"GPIOCOM3_VNN_REQ_STS", BIT(21)},
545 {"GPIOCOM2_VNN_REQ_STS", BIT(22)},
546 {"GPIOCOM1_VNN_REQ_STS", BIT(23)},
547 {"GPIOCOM0_VNN_REQ_STS", BIT(24)},
552 {"ESE_VNN_REQ_STS", BIT(3)},
553 {"DTS0_VNN_REQ_STS", BIT(7)},
554 {"GPIOCOM5_VNN_REQ_STS", BIT(11)},
555 {"FIA1_VNN_REQ_STS", BIT(12)},
560 {"CPU_C10_REQ_STS", BIT(0)},
561 {"TS_OFF_REQ_STS", BIT(1)},
562 {"PNDE_MET_REQ_STS", BIT(2)},
563 {"PCIE_DEEP_PM_REQ_STS", BIT(3)},
564 {"FW_THROTTLE_ALLOWED_REQ_STS", BIT(4)},
565 {"ISH_VNNAON_REQ_STS", BIT(7)},
566 {"IOE_COND_MET_S02I2_0_REQ_STS", BIT(8)},
567 {"IOE_COND_MET_S02I2_1_REQ_STS", BIT(9)},
568 {"IOE_COND_MET_S02I2_2_REQ_STS", BIT(10)},
569 {"PLT_GREATER_REQ_STS", BIT(11)},
570 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)},
571 {"PM_SYNC_STATES_REQ_STS", BIT(14)},
572 {"EA_REQ_STS", BIT(15)},
573 {"DMI_CLKREQ_B_REQ_STS", BIT(16)},
574 {"BRK_EV_EN_REQ_STS", BIT(17)},
575 {"AUTO_DEMO_EN_REQ_STS", BIT(18)},
576 {"ITSS_CLK_SRC_REQ_STS", BIT(19)},
577 {"ARC_IDLE_REQ_STS", BIT(21)},
578 {"DMI_IN_REQ_STS", BIT(22)},
579 {"FIA_DEEP_PM_REQ_STS", BIT(23)},
580 {"XDCI_ATTACHED_REQ_STS", BIT(24)},
581 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)},
582 {"PRE_WAKE0_REQ_STS", BIT(27)},
583 {"PRE_WAKE1_REQ_STS", BIT(28)},
584 {"PRE_WAKE2_EN_REQ_STS", BIT(29)},
585 {"CNVI_V1P05_REQ_STS", BIT(31)},
590 {"LSX_Wake0_STS", BIT(0)},
591 {"LSX_Wake1_STS", BIT(1)},
592 {"LSX_Wake2_STS", BIT(2)},
593 {"LSX_Wake3_STS", BIT(3)},
594 {"LSX_Wake4_STS", BIT(4)},
595 {"LSX_Wake5_STS", BIT(5)},
596 {"LSX_Wake6_STS", BIT(6)},
597 {"LSX_Wake7_STS", BIT(7)},
598 {"Int_Timer_SS_Wake0_STS", BIT(8)},
599 {"Int_Timer_SS_Wake1_STS", BIT(9)},
600 {"Int_Timer_SS_Wake0_STS", BIT(10)},
601 {"Int_Timer_SS_Wake1_STS", BIT(11)},
602 {"Int_Timer_SS_Wake2_STS", BIT(12)},
603 {"Int_Timer_SS_Wake3_STS", BIT(13)},
604 {"Int_Timer_SS_Wake4_STS", BIT(14)},
605 {"Int_Timer_SS_Wake5_STS", BIT(15)},