Lines Matching +full:6 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
47 /* argument: Integer, range is HW-dependant */
49 /* argument: Integer, range is HW-dependant */
51 /* argument: Integer, range is HW-dependant */
53 /* argument: Integer, range is HW-dependant */
55 /* argument: Integer, range is HW-dependant */
75 * struct tegra_function - Tegra pinctrl mux function
87 * struct tegra_pingroup - Tegra pin group
96 * @mux_bit: Mux register bit.
97 * @pupd_reg: Pull-up/down register offset.
98 * @pupd_bank: Pull-up/down register bank.
99 * @pupd_bit: Pull-up/down register bit.
100 * @tri_reg: Tri-state register offset.
101 * @tri_bank: Tri-state register bank.
102 * @tri_bit: Tri-state register bit.
103 * @einput_bit: Enable-input register bit.
104 * @odrain_bit: Open-drain register bit.
105 * @lock_bit: Lock register bit.
106 * @ioreset_bit: IO reset register bit.
107 * @rcv_sel_bit: Receiver select bit.
112 * @hsm_bit: High Speed Mode register bit.
113 * @sfsel_bit: GPIO/SFIO selection register bit.
114 * @schmitt_bit: Schmitt register bit.
115 * @lpmd_bit: Low Power Mode register bit.
116 * @drvdn_bit: Drive Down register bit.
118 * @drvup_bit: Drive Up register bit.
120 * @slwr_bit: Slew Rising register bit.
122 * @slwf_bit: Slew Falling register bit.
124 * @lpdr_bit: Base driver enabling bit.
125 * @drvtype_bit: Drive type register bit.
128 * -1 in a *_reg field means that feature is unsupported for this group.
129 * *_bank and *_reg values are irrelevant when *_reg is -1.
130 * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature.
135 * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
152 s32 mux_bit:6;
153 s32 pupd_bit:6;
154 s32 tri_bit:6;
155 s32 einput_bit:6;
156 s32 odrain_bit:6;
157 s32 lock_bit:6;
158 s32 ioreset_bit:6;
159 s32 rcv_sel_bit:6;
160 s32 hsm_bit:6;
161 s32 sfsel_bit:6;
162 s32 schmitt_bit:6;
163 s32 lpmd_bit:6;
164 s32 drvdn_bit:6;
165 s32 drvup_bit:6;
166 s32 slwr_bit:6;
167 s32 slwf_bit:6;
168 s32 lpdr_bit:6;
169 s32 drvtype_bit:6;
170 s32 drvdn_width:6;
171 s32 drvup_width:6;
172 s32 slwr_width:6;
173 s32 slwf_width:6;
178 * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration