pinctrl/stm32/pinctrl-stm32mp135.c

1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
10 #include "pinctrl-stm32.h"
71 		STM32_FUNCTION(11, "ETH1_PPS_OUT"),
85 		STM32_FUNCTION(11, "ETH1_PPS_OUT"),
128 		STM32_FUNCTION(11, "OTG_HS_SOF"),
142 		STM32_FUNCTION(11, "FMC_NWAIT"),
143 		STM32_FUNCTION(14, "DCMIPP_D0"),
154 		PINCTRL_PIN(11, "PA11"),
160 		STM32_FUNCTION(11, "ETH2_MII_RXD1 ETH2_RGMII_RXD1 ETH2_RMII_RXD1"),
162 		STM32_FUNCTION(14, "ETH2_CLK"),
171 		STM32_FUNCTION(11, "TSC_G1_IO2"),
174 		STM32_FUNCTION(14, "DCMIPP_D1"),
188 		PINCTRL_PIN(14, "PA14"),
193 		STM32_FUNCTION(11, "OTG_HS_SOF"),
205 		STM32_FUNCTION(11, "TSC_G3_IO1"),
208 		STM32_FUNCTION(14, "DCMIPP_D14"),
225 		STM32_FUNCTION(11, "SAI2_D2"),
263 		STM32_FUNCTION(11, "SDMMC2_D2"),
266 		STM32_FUNCTION(14, "UART7_RX"),
279 		STM32_FUNCTION(11, "SDMMC2_D3"),
282 		STM32_FUNCTION(14, "LCD_B6"),
297 		STM32_FUNCTION(14, "LCD_B6"),
312 		STM32_FUNCTION(11, "TSC_G1_IO4"),
315 		STM32_FUNCTION(14, "DCMIPP_D5"),
328 		STM32_FUNCTION(11, "FMC_NCE2"),
330 		STM32_FUNCTION(14, "DCMIPP_D13"),
343 		STM32_FUNCTION(11, "SAI1_D1"),
345 		STM32_FUNCTION(14, "DCMIPP_D6"),
355 		STM32_FUNCTION(11, "SDMMC2_D5"),
358 		STM32_FUNCTION(14, "LCD_DE"),
394 		STM32_FUNCTION(14, "LCD_R3"),
409 		STM32_FUNCTION(14, "LCD_CLK"),
420 		STM32_FUNCTION(11, "SDMMC2_D0"),
422 		STM32_FUNCTION(14, "LCD_R0"),
438 		STM32_FUNCTION(11, "SDMMC2_D1"),
440 		STM32_FUNCTION(14, "LCD_CLK"),
459 		STM32_FUNCTION(11, "ETH1_MII_RX_DV ETH1_RMII_CRS_DV"),
470 		STM32_FUNCTION(11, "SAI2_CK1"),
482 		STM32_FUNCTION(11, "SAI1_MCLK_A"),
523 		STM32_FUNCTION(11, "SDMMC2_D6"),
526 		STM32_FUNCTION(14, "LCD_R6"),
541 		STM32_FUNCTION(11, "SDMMC2_D7"),
557 		STM32_FUNCTION(11, "SAI2_FS_B"),
583 		STM32_FUNCTION(11, "SAI2_MCLK_B"),
595 		STM32_FUNCTION(11, "SAI2_SCK_B"),
604 		STM32_FUNCTION(11, "SAI2_SD_B"),
631 		STM32_FUNCTION(14, "DCMIPP_D1"),
643 		STM32_FUNCTION(14, "DCMIPP_D13"),
668 		STM32_FUNCTION(14, "DCMIPP_D5"),
680 		STM32_FUNCTION(14, "LCD_R4"),
689 		STM32_FUNCTION(14, "LCD_B0"),
701 		STM32_FUNCTION(14, "DCMIPP_D4"),
713 		STM32_FUNCTION(11, "ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"),
725 		STM32_FUNCTION(11, "TSC_G1_IO3"),
726 		STM32_FUNCTION(14, "DCMIPP_D9"),
735 		STM32_FUNCTION(11, "SDMMC2_CDIR"),
738 		STM32_FUNCTION(14, "LCD_CLK"),
750 		STM32_FUNCTION(11, "TSC_G2_IO2"),
753 		STM32_FUNCTION(14, "DCMIPP_VSYNC"),
765 		STM32_FUNCTION(11, "ETH2_RGMII_CLK125"),
768 		STM32_FUNCTION(14, "UART7_RX"),
780 		STM32_FUNCTION(14, "DCMIPP_D6"),
793 		STM32_FUNCTION(11, "TSC_G2_IO4"),
807 		STM32_FUNCTION(14, "DCMIPP_D8"),
828 		STM32_FUNCTION(11, "TSC_G4_IO1"),
831 		STM32_FUNCTION(14, "DCMIPP_D1"),
844 		STM32_FUNCTION(14, "DCMIPP_D3"),
859 		STM32_FUNCTION(11, "ETH2_MII_RXD1 ETH2_RGMII_RXD1 ETH2_RMII_RXD1"),
873 		STM32_FUNCTION(11, "SDMMC2_CK"),
874 		STM32_FUNCTION(14, "LCD_R4"),
889 		STM32_FUNCTION(11, "FMC_NCE2"),
892 		STM32_FUNCTION(14, "DCMIPP_D3"),
903 		STM32_FUNCTION(11, "ETH1_MII_TXD3 ETH1_RGMII_TXD3"),
919 		STM32_FUNCTION(14, "DCMIPP_D7"),
930 		STM32_FUNCTION(14, "LCD_B3"),
951 		STM32_FUNCTION(14, "DCMIPP_D7"),
975 		STM32_FUNCTION(11, "ETH2_MII_TX_ER"),
978 		STM32_FUNCTION(14, "DCMIPP_D10"),
989 		STM32_FUNCTION(11, "TSC_G3_IO2"),
992 		STM32_FUNCTION(14, "DCMIPP_D11"),
1005 		STM32_FUNCTION(14, "DCMIPP_D4"),
1016 		STM32_FUNCTION(11, "QUADSPI_BK2_IO2"),
1018 		STM32_FUNCTION(14, "DCMIPP_D7"),
1030 		STM32_FUNCTION(14, "DCMIPP_D10"),
1041 		STM32_FUNCTION(11, "SDMMC2_D4"),
1043 		STM32_FUNCTION(14, "LCD_R6"),
1054 		STM32_FUNCTION(14, "LCD_B7"),
1069 		STM32_FUNCTION(14, "LCD_G4"),
1088 		STM32_FUNCTION(11, "TSC_G3_IO3"),
1091 		STM32_FUNCTION(14, "DCMIPP_D4"),
1103 		STM32_FUNCTION(14, "DCMIPP_D11"),
1115 		STM32_FUNCTION(14, "LCD_R7"),
1125 		STM32_FUNCTION(11, "ETH1_RGMII_CLK125"),
1140 		STM32_FUNCTION(11, "QUADSPI_BK1_IO0"),
1141 		STM32_FUNCTION(14, "DCMIPP_D15"),
1155 		STM32_FUNCTION(11, "QUADSPI_BK1_IO1"),
1171 		STM32_FUNCTION(14, "DCMIPP_HSYNC"),
1191 		STM32_FUNCTION(11, "ETH1_MII_TX_ER"),
1221 		STM32_FUNCTION(11, "TSC_G4_IO2"),
1223 		STM32_FUNCTION(14, "DCMIPP_PIXCLK"),
1237 		STM32_FUNCTION(11, "ETH2_MII_TXD2 ETH2_RGMII_TXD2"),
1247 		STM32_FUNCTION(11, "SAI2_MCLK_B"),
1249 		STM32_FUNCTION(14, "DCMIPP_D1"),
1259 		STM32_FUNCTION(11, "ETH2_RGMII_GTX_CLK"),
1262 		STM32_FUNCTION(14, "DCMIPP_D15"),
1273 		STM32_FUNCTION(11, "SDMMC2_D123DIR"),
1276 		STM32_FUNCTION(14, "DCMIPP_D8"),
1285 		STM32_FUNCTION(11, "ETH2_MDC"),
1288 		STM32_FUNCTION(14, "DCMIPP_VSYNC"),
1301 		STM32_FUNCTION(11, "SDMMC2_CMD"),
1303 		STM32_FUNCTION(14, "LCD_DE"),
1315 		STM32_FUNCTION(11, "SDMMC2_CKIN"),
1317 		STM32_FUNCTION(14, "LCD_R5"),
1331 		STM32_FUNCTION(11, "QUADSPI_BK2_IO2"),
1334 		STM32_FUNCTION(14, "ETH2_CLK"),
1346 		STM32_FUNCTION(11, "FMC_NE2"),
1348 		STM32_FUNCTION(14, "DCMIPP_VSYNC"),
1358 		STM32_FUNCTION(11, "QUADSPI_BK2_IO1"),
1360 		STM32_FUNCTION(14, "DCMIPP_D2"),
1370 		STM32_FUNCTION(11, "ETH2_MII_TXD1 ETH2_RGMII_TXD1 ETH2_RMII_TXD1"),
1372 		STM32_FUNCTION(14, "DCMIPP_D14"),
1385 		STM32_FUNCTION(11, "ETH2_PHY_INTN"),
1404 		STM32_FUNCTION(11, "SAI2_SD_A"),
1414 		STM32_FUNCTION(11, "ETH2_PHY_INTN"),
1416 		STM32_FUNCTION(14, "DCMIPP_D10"),
1439 		STM32_FUNCTION(11, "ETH2_MII_CRS"),
1442 		STM32_FUNCTION(14, "ETH2_RGMII_CLK125"),
1452 		STM32_FUNCTION(11, "ETH1_MII_COL"),
1455 		STM32_FUNCTION(14, "QUADSPI_BK1_IO0"),
1479 		STM32_FUNCTION(11, "ETH1_PHY_INTN"),
1482 		STM32_FUNCTION(14, "QUADSPI_BK1_NCS"),
1492 		STM32_FUNCTION(11, "ETH2_MII_TX_CLK"),
1494 		STM32_FUNCTION(14, "QUADSPI_BK1_IO3"),
1507 		STM32_FUNCTION(14, "DCMIPP_HSYNC"),
1523 		STM32_FUNCTION(14, "DCMIPP_D9"),
1538 		STM32_FUNCTION(14, "LCD_HSYNC"),
1568 		STM32_FUNCTION(11, "SAI1_CK2"),
1571 		STM32_FUNCTION(14, "DCMIPP_D3"),
1583 		STM32_FUNCTION(14, "LCD_G3"),
1595 		STM32_FUNCTION(14, "DCMIPP_D2"),
1657 		.compatible = "st,stm32mp135-pinctrl",
1670 		.name = "stm32mp135-pinctrl",