Lines Matching +full:0 +full:xfffffe00
34 #define PAD_FUNCTION_EN_1 0x668
35 #define PAD_FUNCTION_EN_2 0x66C
36 #define PAD_FUNCTION_EN_3 0x670
37 #define PAD_FUNCTION_EN_4 0x674
38 #define PAD_FUNCTION_EN_5 0x690
39 #define PAD_FUNCTION_EN_6 0x694
40 #define PAD_FUNCTION_EN_7 0x698
41 #define PAD_FUNCTION_EN_8 0x69C
44 #define PAD_SHARED_IP_EN_1 0x6A0
45 #define PAD_SHARED_IP_EN_2 0x6A4
53 #define PADS_AS_GPIO_REG0_MASK 0xFFFFFFFE
54 #define PADS_AS_GPIO_REGS_MASK 0xFFFFFFFF
55 #define PADS_AS_GPIO_REG7_MASK 0x07FFFFFF
58 #define FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK 0x00000FFE
59 #define UART0_ENH_AND_GPT_REG0_MASK 0x0003F000
60 #define PWM1_AND_KBD_COL5_REG0_MASK 0x00040000
61 #define I2C1_REG0_MASK 0x01080000
62 #define SPDIF_IN_REG0_MASK 0x00100000
63 #define PWM2_AND_GPT0_TMR0_CPT_REG0_MASK 0x00400000
64 #define PWM3_AND_GPT0_TMR1_CLK_REG0_MASK 0x00800000
65 #define PWM0_AND_SSP0_CS1_REG0_MASK 0x02000000
66 #define VIP_AND_CAM3_REG0_MASK 0xFC200000
67 #define VIP_AND_CAM3_REG1_MASK 0x0000000F
68 #define VIP_REG1_MASK 0x00001EF0
69 #define VIP_AND_CAM2_REG1_MASK 0x007FE100
70 #define VIP_AND_CAM1_REG1_MASK 0xFF800000
71 #define VIP_AND_CAM1_REG2_MASK 0x00000003
72 #define VIP_AND_CAM0_REG2_MASK 0x00001FFC
73 #define SMI_REG2_MASK 0x0021E000
74 #define SSP0_REG2_MASK 0x001E0000
75 #define TS_AND_SSP0_CS2_REG2_MASK 0x00400000
76 #define UART0_REG2_MASK 0x01800000
77 #define UART1_REG2_MASK 0x06000000
78 #define I2S_IN_REG2_MASK 0xF8000000
79 #define DEVS_GRP_AND_MIPHY_DBG_REG3_MASK 0x000001FE
80 #define I2S_OUT_REG3_MASK 0x000001EF
81 #define I2S_IN_REG3_MASK 0x00000010
82 #define GMAC_REG3_MASK 0xFFFFFE00
83 #define GMAC_REG4_MASK 0x0000001F
84 #define DEVS_GRP_AND_MIPHY_DBG_REG4_MASK 0x7FFFFF20
85 #define SSP0_CS3_REG4_MASK 0x00000020
86 #define I2C0_REG4_MASK 0x000000C0
87 #define CEC0_REG4_MASK 0x00000100
88 #define CEC1_REG4_MASK 0x00000200
89 #define SPDIF_OUT_REG4_MASK 0x00000400
90 #define CLCD_REG4_MASK 0x7FFFF800
91 #define CLCD_AND_ARM_TRACE_REG4_MASK 0x80000000
92 #define CLCD_AND_ARM_TRACE_REG5_MASK 0xFFFFFFFF
93 #define CLCD_AND_ARM_TRACE_REG6_MASK 0x00000001
94 #define FSMC_PNOR_AND_MCIF_REG6_MASK 0x073FFFFE
95 #define MCIF_REG6_MASK 0xF8C00000
96 #define MCIF_REG7_MASK 0x000043FF
97 #define FSMC_8BIT_REG7_MASK 0x07FFBC00
100 #define PERIP_CFG 0x42C
102 #define SSP_CS_CTL_HW 0
108 #define SSP_CS_SEL_CS0 0
114 #define I2S_CHNL_2_0 (0)
130 #define MCIF_SEL_SHIFT 0
132 #define GMAC_CLK_CFG 0x248
133 #define GMAC_PHY_IF_GMII_VAL (0 << 3)
138 #define GMAC_PHY_INPUT_ENB_VAL 0
142 #define GMAC_PHY_125M_PAD_VAL 0
146 #define GMAC_PHY_INPUT_CLK_SHIFT 0
148 #define PCIE_SATA_CFG 0x424
158 #define PCIE_SATA_SEL_PCIE (0)
160 #define SATA_PCIE_CFG_MASK 0xF1F
169 /* Write 0 to enable FSMC_16_BIT */
170 #define KBD_ROW_COL_MASK (1 << 0)
172 /* Write 0 to enable UART0_ENH */
175 /* Write 0 to enable PWM1 */
178 /* Write 0 to enable PWM2 */
181 /* Write 0 to enable PWM3 */
184 /* Write 0 to enable PWM0 */
187 /* Write 0 to enable VIP */
190 /* Write 0 to enable VIP */
193 /* Write 0 to enable VIP */
196 /* Write 0 to enable VIP */
199 /* Write 0 to enable TS */
202 /* Write 0 to enable FSMC PNOR */
205 /* Write 0 to enable CLCD */
208 /* Write 0 to enable I2S, SSP0_CS2, CEC0, 1, SPDIF out, CLCD */
220 .val = 0x0,
224 .val = 0x0,
228 .val = 0x0,
232 .val = 0x0,
236 .val = 0x0,
240 .val = 0x0,
244 .val = 0x0,
248 .val = 0x0,
301 static const unsigned fsmc_16bit_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 };
306 .val = 0,
337 .val = 0,
369 static const unsigned keyboard_row_col_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
549 .val = 0,
578 .val = 0,
607 .val = 0,
636 .val = 0,
699 .val = 0,
729 .val = 0,
763 .val = 0,
793 .val = 0,
1163 .val = 0,
1663 .val = 0,
1699 .val = 0,
1703 .val = 0x0,
1707 .val = 0x0,
1711 .val = 0x0,
1992 val &= ~(0x1 << bitoffset); in gpio_request_endisable()
1994 val |= 0x1 << bitoffset; in gpio_request_endisable()