Lines Matching +full:bank +full:- +full:number
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
70 * enum pud_index - Possible index values to access the pud_val array.
84 * enum eint_type - possible external interrupt types.
85 * @EINT_TYPE_NONE: bank does not support external interrupts
86 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
87 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
88 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
91 * in a pin bank can support external gpio interrupts or external wakeup
104 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
125 * struct samsung_pin_bank_type: pin bank type description
135 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
136 * @type: type of the bank (register offsets and bitfield widths)
137 * @pctl_offset: starting offset of the pin-bank registers.
138 * @pctl_res_idx: index of base address for pin-bank registers.
139 * @nr_pins: number of pins included in this bank.
141 * @eint_type: type of the external interrupt supported by the bank.
143 * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
144 * @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank.
145 * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
146 * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
147 * @name: name to be prefixed for each pin in this pin bank.
165 * struct samsung_pin_bank: represent a controller pin-bank.
166 * @type: type of the bank (register offsets and bitfield widths)
167 * @pctl_base: base address of the pin-bank registers
168 * @pctl_offset: starting offset of the pin-bank registers.
169 * @nr_pins: number of pins included in this bank.
170 * @eint_base: base address of the pin-bank EINT registers.
172 * @eint_type: type of the external interrupt supported by the bank.
174 * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
175 * @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank.
176 * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
177 * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
178 * @name: name to be prefixed for each pin in this pin bank.
179 * @id: id of the bank, propagated to the pin range.
180 * @pin_base: starting pin number of the bank.
181 * @soc_priv: per-bank private data for SoC-specific code.
182 * @of_node: OF node of the bank.
184 * @irq_domain: IRQ domain of the bank.
185 * @gpio_chip: GPIO chip of the bank.
186 * @grange: linux gpio pin range supported by this bank.
188 * @slock: spinlock protecting bank registers
221 * struct samsung_retention_data: runtime pin-bank retention control data.
223 * @nr_regs: number of registers in @regs array.
225 * @refcnt: atomic counter if retention control affects more than one bank.
241 * struct samsung_retention_data: represent a pin-bank retention control data.
243 * @nr_regs: number of registers in @regs array.
245 * @refcnt: atomic counter if retention control affects more than one bank.
260 * @nr_banks: number of pin banks.
261 * @nr_ext_resources: number of the extra base address for pin banks.
292 * to each bank samsung_pin_bank->pctl_base and used on legacy
296 * @irq: interrpt number used by the controller to notify gpio interrupts.
302 * @nr_groups: number of such pin groups.
304 * @nr_function: number of such pin functions.
305 * @nr_pins: number of pins supported by the controller.
352 * @num_pins: number of pins included in this group.
353 * @func: the function number to be programmed when selected.
366 * @num_groups: number of groups included in @groups.