33 #define SVC_GROUP_MASK		0xf
34 #define SVC_NUM_MASK		0xf
38 #define EINT12CON_REG		0x200
39 #define EINT12MASK_REG		0x240
40 #define EINT12PEND_REG		0x260
50 #define SERVICE_REG		0x284
51 #define SERVICEPEND_REG		0x288
53 #define EINT0CON0_REG		0x900
54 #define EINT0MASK_REG		0x920
55 #define EINT0PEND_REG		0x924
58 #define EINT_LEVEL_LOW		0
63 #define EINT_CON_MASK		0xF
66 #define S3C_PIN_PULL_DISABLE	0
71 	.fld_width = { 4, 1, 2, 0, 2, 2, },
72 	.reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
77 	.reg_offset = { 0x00, 0x04, 0x08, },
81 	.fld_width = { 4, 1, 2, 0, 2, 2, },
82 	.reg_offset = { 0x00, 0x08, 0x0c, 0, 0x10, 0x14, },
87 	.reg_offset = { 0x00, 0x08, 0x0c, },
91 	.fld_width = { 2, 1, 2, 0, 2, 2, },
92 	.reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
97 	.reg_offset = { 0x00, 0x04, 0x08, },
362 	if (trigger < 0) {  in s3c64xx_gpio_irq_set_type()
381 	return 0;  in s3c64xx_gpio_irq_set_type()
407 	return 0;  in s3c64xx_gpio_irq_map()
442 				group = 0;  in s3c64xx_eint_gpio_irq()
475 	nr_domains = 0;  in s3c64xx_eint_gpio_init()
477 	for (i = 0; i < d->nr_banks; ++i, ++bank) {  in s3c64xx_eint_gpio_init()
504 	nr_domains = 0;  in s3c64xx_eint_gpio_init()
505 	for (i = 0; i < d->nr_banks; ++i, ++bank) {  in s3c64xx_eint_gpio_init()
514 	return 0;  in s3c64xx_eint_gpio_init()
568 	if (trigger < 0) {  in s3c64xx_eint0_irq_set_type()
591 	return 0;  in s3c64xx_eint0_irq_set_type()
639 	s3c64xx_irq_demux_eint(desc, 0xf);  in s3c64xx_demux_eint0_3()
644 	s3c64xx_irq_demux_eint(desc, 0xff0);  in s3c64xx_demux_eint4_11()
649 	s3c64xx_irq_demux_eint(desc, 0xff000);  in s3c64xx_demux_eint12_19()
654 	s3c64xx_irq_demux_eint(desc, 0xff00000);  in s3c64xx_demux_eint20_27()
677 	return 0;  in s3c64xx_eint0_irq_map()
723 	for (i = 0; i < NUM_EINT0_IRQ; ++i) {  in s3c64xx_eint_eint0_init()
740 	for (i = 0; i < d->nr_banks; ++i, ++bank) {  in s3c64xx_eint_eint0_init()
768 		for (pin = 0; mask; ++pin, mask >>= 1) {  in s3c64xx_eint_eint0_init()
778 	return 0;  in s3c64xx_eint_eint0_init()
781 /* pin banks of s3c64xx pin-controller 0 */
783 	PIN_BANK_4BIT_EINTG(8, 0x000, "gpa", 0),
784 	PIN_BANK_4BIT_EINTG(7, 0x020, "gpb", 8),
785 	PIN_BANK_4BIT_EINTG(8, 0x040, "gpc", 16),
786 	PIN_BANK_4BIT_EINTG(5, 0x060, "gpd", 32),
787 	PIN_BANK_4BIT(5, 0x080, "gpe"),
788 	PIN_BANK_2BIT_EINTG(16, 0x0a0, "gpf", 48, 0x3fff),
789 	PIN_BANK_4BIT_EINTG(7, 0x0c0, "gpg", 64),
790 	PIN_BANK_4BIT2_EINTG(10, 0x0e0, "gph", 80),
791 	PIN_BANK_2BIT(16, 0x100, "gpi"),
792 	PIN_BANK_2BIT(12, 0x120, "gpj"),
793 	PIN_BANK_4BIT2_ALIVE(16, 0x800, "gpk"),
794 	PIN_BANK_4BIT2_EINTW(15, 0x810, "gpl", 16, 0x7f00),
795 	PIN_BANK_4BIT_EINTW(6, 0x820, "gpm", 23, 0x1f),
796 	PIN_BANK_2BIT_EINTW(16, 0x830, "gpn", 0),
797 	PIN_BANK_2BIT_EINTG(16, 0x140, "gpo", 96, 0xffff),
798 	PIN_BANK_2BIT_EINTG(15, 0x160, "gpp", 112, 0x7fff),
799 	PIN_BANK_2BIT_EINTG(9, 0x180, "gpq", 128, 0x1ff),