8 #define DRV_NAME "sh-pfc"
39 	struct sh_pfc *pfc;  member
49 	return pmx->pfc->info->nr_groups;  in sh_pfc_get_groups_count()
57 	return pmx->pfc->info->groups[selector].name;  in sh_pfc_get_group_name()
65 	*pins = pmx->pfc->info->groups[selector].pins;  in sh_pfc_get_group_pins()
66 	*num_pins = pmx->pfc->info->groups[selector].nr_pins;  in sh_pfc_get_group_pins()
104 	struct device *dev = pmx->pfc->dev;  in sh_pfc_dt_subnode_to_map()
242 	struct device *dev = pmx->pfc->dev;  in sh_pfc_dt_node_to_map()
294 	return pmx->pfc->info->nr_functions;  in sh_pfc_get_functions_count()
302 	return pmx->pfc->info->functions[selector].name;  in sh_pfc_get_function_name()
312 	*groups = pmx->pfc->info->functions[selector].groups;  in sh_pfc_get_function_groups()
313 	*num_groups = pmx->pfc->info->functions[selector].nr_groups;  in sh_pfc_get_function_groups()
322 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_func_set_mux()  local
323 	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];  in sh_pfc_func_set_mux()
330 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_func_set_mux()
333 		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);  in sh_pfc_func_set_mux()
345 		ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);  in sh_pfc_func_set_mux()
352 		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);  in sh_pfc_func_set_mux()
359 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_func_set_mux()
368 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_gpio_request_enable()  local
369 	int idx = sh_pfc_get_pin_index(pfc, offset);  in sh_pfc_gpio_request_enable()
374 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_gpio_request_enable()
376 	if (!pfc->gpio && !cfg->mux_mark) {  in sh_pfc_gpio_request_enable()
380 		const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_gpio_request_enable()
382 		ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);  in sh_pfc_gpio_request_enable()
392 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_gpio_request_enable()
402 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_gpio_disable_free()  local
403 	int idx = sh_pfc_get_pin_index(pfc, offset);  in sh_pfc_gpio_disable_free()
407 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_gpio_disable_free()
411 		sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION);  in sh_pfc_gpio_disable_free()
412 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_gpio_disable_free()
421 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_gpio_set_direction()  local
423 	int idx = sh_pfc_get_pin_index(pfc, offset);  in sh_pfc_gpio_set_direction()
424 	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_gpio_set_direction()
438 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_gpio_set_direction()
439 	ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);  in sh_pfc_gpio_set_direction()
440 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_gpio_set_direction()
457 static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc,  in sh_pfc_pinconf_find_drive_strength_reg()  argument
464 	for (reg = pfc->info->drive_regs; reg->reg; ++reg) {  in sh_pfc_pinconf_find_drive_strength_reg()
480 static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc,  in sh_pfc_pinconf_get_drive_strength()  argument
488 	reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);  in sh_pfc_pinconf_get_drive_strength()
492 	val = (sh_pfc_read(pfc, reg) >> offset) & GENMASK(size - 1, 0);  in sh_pfc_pinconf_get_drive_strength()
500 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,  in sh_pfc_pinconf_set_drive_strength()  argument
510 	reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);  in sh_pfc_pinconf_set_drive_strength()
524 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_set_drive_strength()
526 	val = sh_pfc_read(pfc, reg);  in sh_pfc_pinconf_set_drive_strength()
530 	sh_pfc_write(pfc, reg, val);  in sh_pfc_pinconf_set_drive_strength()
532 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_set_drive_strength()
538 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,  in sh_pfc_pinconf_validate()  argument
541 	int idx = sh_pfc_get_pin_index(pfc, _pin);  in sh_pfc_pinconf_validate()
542 	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_pinconf_validate()
569 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_pinconf_get()  local
574 	if (!sh_pfc_pinconf_validate(pfc, _pin, param))  in sh_pfc_pinconf_get()
583 		if (!pfc->info->ops || !pfc->info->ops->get_bias)  in sh_pfc_pinconf_get()
586 		spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_get()
587 		bias = pfc->info->ops->get_bias(pfc, _pin);  in sh_pfc_pinconf_get()
588 		spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_get()
600 		ret = sh_pfc_pinconf_get_drive_strength(pfc, _pin);  in sh_pfc_pinconf_get()
609 		int idx = sh_pfc_get_pin_index(pfc, _pin);  in sh_pfc_pinconf_get()
610 		const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_pinconf_get()
615 		if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)  in sh_pfc_pinconf_get()
618 		bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl);  in sh_pfc_pinconf_get()
622 		val = sh_pfc_read(pfc, pocctrl);  in sh_pfc_pinconf_get()
644 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_pinconf_set()  local
652 		if (!sh_pfc_pinconf_validate(pfc, _pin, param))  in sh_pfc_pinconf_set()
659 			if (!pfc->info->ops || !pfc->info->ops->set_bias)  in sh_pfc_pinconf_set()
662 			spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_set()
663 			pfc->info->ops->set_bias(pfc, _pin, param);  in sh_pfc_pinconf_set()
664 			spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_set()
673 			ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);  in sh_pfc_pinconf_set()
682 			int idx = sh_pfc_get_pin_index(pfc, _pin);  in sh_pfc_pinconf_set()
683 			const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_pinconf_set()
688 			if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)  in sh_pfc_pinconf_set()
691 			bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl);  in sh_pfc_pinconf_set()
702 			spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_set()
703 			val = sh_pfc_read(pfc, pocctrl);  in sh_pfc_pinconf_set()
708 			sh_pfc_write(pfc, pocctrl, val);  in sh_pfc_pinconf_set()
709 			spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_set()
731 	pins = pmx->pfc->info->groups[group].pins;  in sh_pfc_pinconf_group_set()
732 	num_pins = pmx->pfc->info->groups[group].nr_pins;  in sh_pfc_pinconf_group_set()
751 /* PFC ranges -> pinctrl pin descs */
752 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)  in sh_pfc_map_pins()  argument
757 	pmx->pins = devm_kcalloc(pfc->dev,  in sh_pfc_map_pins()
758 				 pfc->info->nr_pins, sizeof(*pmx->pins),  in sh_pfc_map_pins()
763 	pmx->configs = devm_kcalloc(pfc->dev,  in sh_pfc_map_pins()
764 				    pfc->info->nr_pins, sizeof(*pmx->configs),  in sh_pfc_map_pins()
769 	for (i = 0; i < pfc->info->nr_pins; ++i) {  in sh_pfc_map_pins()
770 		const struct sh_pfc_pin *info = &pfc->info->pins[i];  in sh_pfc_map_pins()
781 int sh_pfc_register_pinctrl(struct sh_pfc *pfc)  in sh_pfc_register_pinctrl()  argument
786 	pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);  in sh_pfc_register_pinctrl()
790 	pmx->pfc = pfc;  in sh_pfc_register_pinctrl()
792 	ret = sh_pfc_map_pins(pfc, pmx);  in sh_pfc_register_pinctrl()
802 	pmx->pctl_desc.npins = pfc->info->nr_pins;  in sh_pfc_register_pinctrl()
804 	ret = devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx,  in sh_pfc_register_pinctrl()
807 		dev_err(pfc->dev, "could not register: %i\n", ret);  in sh_pfc_register_pinctrl()
835 unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)  in rcar_pinmux_get_bias()  argument
840 	reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);  in rcar_pinmux_get_bias()
845 		if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))  in rcar_pinmux_get_bias()
847 		else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit)))  in rcar_pinmux_get_bias()
852 		if (sh_pfc_read(pfc, reg->pud) & BIT(bit))  in rcar_pinmux_get_bias()
859 void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,  in rcar_pinmux_set_bias()  argument
866 	reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);  in rcar_pinmux_set_bias()
871 		enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);  in rcar_pinmux_set_bias()
876 				updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);  in rcar_pinmux_set_bias()
880 				sh_pfc_write(pfc, reg->pud, updown);  in rcar_pinmux_set_bias()
883 		sh_pfc_write(pfc, reg->puen, enable);  in rcar_pinmux_set_bias()
885 		enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);  in rcar_pinmux_set_bias()
889 		sh_pfc_write(pfc, reg->pud, enable);  in rcar_pinmux_set_bias()
898 unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)  in rmobile_pinmux_get_bias()  argument
900 	void __iomem *reg = pfc->windows->virt +  in rmobile_pinmux_get_bias()
901 			    pfc->info->ops->pin_to_portcr(pin);  in rmobile_pinmux_get_bias()
915 void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,  in rmobile_pinmux_set_bias()  argument
918 	void __iomem *reg = pfc->windows->virt +  in rmobile_pinmux_set_bias()
919 			    pfc->info->ops->pin_to_portcr(pin);  in rmobile_pinmux_set_bias()