Lines Matching full:pctrl
142 static void rzv2m_pinctrl_set_pfc_mode(struct rzv2m_pinctrl *pctrl, in rzv2m_pinctrl_set_pfc_mode() argument
148 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 1); in rzv2m_pinctrl_set_pfc_mode()
149 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 1); in rzv2m_pinctrl_set_pfc_mode()
152 addr = pctrl->base + PFSEL(port) + (pin / 4) * 4; in rzv2m_pinctrl_set_pfc_mode()
156 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 0); in rzv2m_pinctrl_set_pfc_mode()
157 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 0); in rzv2m_pinctrl_set_pfc_mode()
164 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzv2m_pinctrl_set_mux() local
181 dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", in rzv2m_pinctrl_set_mux()
184 rzv2m_pinctrl_set_pfc_mode(pctrl, RZV2M_PIN_ID_TO_PORT(pins[i]), in rzv2m_pinctrl_set_mux()
218 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzv2m_dt_subnode_to_map() local
242 dev_err(pctrl->dev, "Invalid pins list in DT\n"); in rzv2m_dt_subnode_to_map()
252 dev_err(pctrl->dev, in rzv2m_dt_subnode_to_map()
262 dev_err(pctrl->dev, "DT node must contain a config\n"); in rzv2m_dt_subnode_to_map()
295 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); in rzv2m_dt_subnode_to_map()
296 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), in rzv2m_dt_subnode_to_map()
298 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); in rzv2m_dt_subnode_to_map()
316 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", in rzv2m_dt_subnode_to_map()
326 mutex_lock(&pctrl->mutex); in rzv2m_dt_subnode_to_map()
346 mutex_unlock(&pctrl->mutex); in rzv2m_dt_subnode_to_map()
353 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); in rzv2m_dt_subnode_to_map()
360 mutex_unlock(&pctrl->mutex); in rzv2m_dt_subnode_to_map()
389 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzv2m_dt_node_to_map() local
414 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); in rzv2m_dt_node_to_map()
423 static int rzv2m_validate_gpio_pin(struct rzv2m_pinctrl *pctrl, in rzv2m_validate_gpio_pin() argument
430 if (bit >= pincount || port >= pctrl->data->n_port_pins) in rzv2m_validate_gpio_pin()
433 data = pctrl->data->port_pin_configs[port]; in rzv2m_validate_gpio_pin()
440 static void rzv2m_rmw_pin_config(struct rzv2m_pinctrl *pctrl, u32 offset, in rzv2m_rmw_pin_config() argument
443 void __iomem *addr = pctrl->base + offset; in rzv2m_rmw_pin_config()
447 spin_lock_irqsave(&pctrl->lock, flags); in rzv2m_rmw_pin_config()
450 spin_unlock_irqrestore(&pctrl->lock, flags); in rzv2m_rmw_pin_config()
457 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzv2m_pinctrl_pinconf_get() local
459 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzv2m_pinctrl_pinconf_get()
479 if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit)) in rzv2m_pinctrl_pinconf_get()
495 switch ((readl(pctrl->base + PUPD(port)) >> bit) & PUPD_MASK) { in rzv2m_pinctrl_pinconf_get()
518 val = (readl(pctrl->base + DRV(port)) >> bit) & DRV_MASK; in rzv2m_pinctrl_pinconf_get()
544 arg = readl(pctrl->base + SR(port)) & BIT(bit); in rzv2m_pinctrl_pinconf_get()
561 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzv2m_pinctrl_pinconf_set() local
562 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzv2m_pinctrl_pinconf_set()
583 if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit)) in rzv2m_pinctrl_pinconf_set()
610 rzv2m_rmw_pin_config(pctrl, PUPD(port), bit, PUPD_MASK, val); in rzv2m_pinctrl_pinconf_set()
649 rzv2m_rmw_pin_config(pctrl, DRV(port), bit, DRV_MASK, index); in rzv2m_pinctrl_pinconf_set()
659 rzv2m_writel_we(pctrl->base + SR(port), bit, !arg); in rzv2m_pinctrl_pinconf_set()
748 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); in rzv2m_gpio_request() local
757 rzv2m_pinctrl_set_pfc_mode(pctrl, port, bit, 0); in rzv2m_gpio_request()
762 static void rzv2m_gpio_set_direction(struct rzv2m_pinctrl *pctrl, u32 port, in rzv2m_gpio_set_direction() argument
765 rzv2m_writel_we(pctrl->base + OE(port), bit, output); in rzv2m_gpio_set_direction()
766 rzv2m_writel_we(pctrl->base + IE(port), bit, !output); in rzv2m_gpio_set_direction()
771 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); in rzv2m_gpio_get_direction() local
775 if (!(readl(pctrl->base + IE(port)) & BIT(bit))) in rzv2m_gpio_get_direction()
784 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); in rzv2m_gpio_direction_input() local
788 rzv2m_gpio_set_direction(pctrl, port, bit, false); in rzv2m_gpio_direction_input()
796 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); in rzv2m_gpio_set() local
800 rzv2m_writel_we(pctrl->base + DO(port), bit, !!value); in rzv2m_gpio_set()
806 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); in rzv2m_gpio_direction_output() local
811 rzv2m_gpio_set_direction(pctrl, port, bit, true); in rzv2m_gpio_direction_output()
818 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); in rzv2m_gpio_get() local
824 return !!(readl(pctrl->base + DI(port)) & BIT(bit)); in rzv2m_gpio_get()
826 return !!(readl(pctrl->base + DO(port)) & BIT(bit)); in rzv2m_gpio_get()
929 static int rzv2m_gpio_register(struct rzv2m_pinctrl *pctrl) in rzv2m_gpio_register() argument
931 struct device_node *np = pctrl->dev->of_node; in rzv2m_gpio_register()
932 struct gpio_chip *chip = &pctrl->gpio_chip; in rzv2m_gpio_register()
933 const char *name = dev_name(pctrl->dev); in rzv2m_gpio_register()
939 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); in rzv2m_gpio_register()
944 of_args.args[2] != pctrl->data->n_port_pins) { in rzv2m_gpio_register()
945 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); in rzv2m_gpio_register()
949 chip->names = pctrl->data->port_pins; in rzv2m_gpio_register()
958 chip->parent = pctrl->dev; in rzv2m_gpio_register()
963 pctrl->gpio_range.id = 0; in rzv2m_gpio_register()
964 pctrl->gpio_range.pin_base = 0; in rzv2m_gpio_register()
965 pctrl->gpio_range.base = 0; in rzv2m_gpio_register()
966 pctrl->gpio_range.npins = chip->ngpio; in rzv2m_gpio_register()
967 pctrl->gpio_range.name = chip->label; in rzv2m_gpio_register()
968 pctrl->gpio_range.gc = chip; in rzv2m_gpio_register()
969 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); in rzv2m_gpio_register()
971 dev_err(pctrl->dev, "failed to add GPIO controller\n"); in rzv2m_gpio_register()
975 dev_dbg(pctrl->dev, "Registered gpio controller\n"); in rzv2m_gpio_register()
980 static int rzv2m_pinctrl_register(struct rzv2m_pinctrl *pctrl) in rzv2m_pinctrl_register() argument
987 pctrl->desc.name = DRV_NAME; in rzv2m_pinctrl_register()
988 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; in rzv2m_pinctrl_register()
989 pctrl->desc.pctlops = &rzv2m_pinctrl_pctlops; in rzv2m_pinctrl_register()
990 pctrl->desc.pmxops = &rzv2m_pinctrl_pmxops; in rzv2m_pinctrl_register()
991 pctrl->desc.confops = &rzv2m_pinctrl_confops; in rzv2m_pinctrl_register()
992 pctrl->desc.owner = THIS_MODULE; in rzv2m_pinctrl_register()
994 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); in rzv2m_pinctrl_register()
998 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, in rzv2m_pinctrl_register()
1003 pctrl->pins = pins; in rzv2m_pinctrl_register()
1004 pctrl->desc.pins = pins; in rzv2m_pinctrl_register()
1006 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { in rzv2m_pinctrl_register()
1008 pins[i].name = pctrl->data->port_pins[i]; in rzv2m_pinctrl_register()
1011 pin_data[i] = pctrl->data->port_pin_configs[j]; in rzv2m_pinctrl_register()
1015 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { in rzv2m_pinctrl_register()
1016 unsigned int index = pctrl->data->n_port_pins + i; in rzv2m_pinctrl_register()
1019 pins[index].name = pctrl->data->dedicated_pins[i].name; in rzv2m_pinctrl_register()
1020 pin_data[index] = pctrl->data->dedicated_pins[i].config; in rzv2m_pinctrl_register()
1024 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, in rzv2m_pinctrl_register()
1025 &pctrl->pctl); in rzv2m_pinctrl_register()
1027 dev_err(pctrl->dev, "pinctrl registration failed\n"); in rzv2m_pinctrl_register()
1031 ret = pinctrl_enable(pctrl->pctl); in rzv2m_pinctrl_register()
1033 dev_err(pctrl->dev, "pinctrl enable failed\n"); in rzv2m_pinctrl_register()
1037 ret = rzv2m_gpio_register(pctrl); in rzv2m_pinctrl_register()
1039 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); in rzv2m_pinctrl_register()
1048 struct rzv2m_pinctrl *pctrl; in rzv2m_pinctrl_probe() local
1052 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in rzv2m_pinctrl_probe()
1053 if (!pctrl) in rzv2m_pinctrl_probe()
1056 pctrl->dev = &pdev->dev; in rzv2m_pinctrl_probe()
1058 pctrl->data = of_device_get_match_data(&pdev->dev); in rzv2m_pinctrl_probe()
1059 if (!pctrl->data) in rzv2m_pinctrl_probe()
1062 pctrl->base = devm_platform_ioremap_resource(pdev, 0); in rzv2m_pinctrl_probe()
1063 if (IS_ERR(pctrl->base)) in rzv2m_pinctrl_probe()
1064 return PTR_ERR(pctrl->base); in rzv2m_pinctrl_probe()
1066 clk = devm_clk_get_enabled(pctrl->dev, NULL); in rzv2m_pinctrl_probe()
1068 return dev_err_probe(pctrl->dev, PTR_ERR(clk), in rzv2m_pinctrl_probe()
1071 spin_lock_init(&pctrl->lock); in rzv2m_pinctrl_probe()
1072 mutex_init(&pctrl->mutex); in rzv2m_pinctrl_probe()
1074 platform_set_drvdata(pdev, pctrl); in rzv2m_pinctrl_probe()
1076 ret = rzv2m_pinctrl_register(pctrl); in rzv2m_pinctrl_probe()
1080 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); in rzv2m_pinctrl_probe()