Lines Matching +full:r9a07g044 +full:- +full:pinctrl
1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
29 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
35 #define DRV_NAME "pinctrl-rzg2l"
60 #define PIN_CFG_NOD BIT(15) /* N-ch Open Drain */
61 #define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */
105 #define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f))
178 { "renesas,output-impedance", RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, 1 },
183 PCONFDUMP(RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, "output-impedance", "x", true),
215 * struct rzg2l_register_offsets - specific register offsets
227 * enum rzg2l_iolh_index - starting indices in IOLH specific arrays
244 * struct rzg2l_hwcfg - hardware configuration data structure
298 * struct rzg2l_pinctrl_pin_settings - pin data
308 * struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume)
368 for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) { in rzg2l_pinctrl_get_variable_pin_cfg()
369 u64 cfg = pctrl->data->variable_pin_cfg[i]; in rzg2l_pinctrl_get_variable_pin_cfg()
435 writeb(val, pctrl->base + offset); in rzg2l_pmc_writeb()
440 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; in rzv2h_pmc_writeb()
443 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_pmc_writeb()
444 writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr); in rzv2h_pmc_writeb()
445 writeb(val, pctrl->base + offset); in rzv2h_pmc_writeb()
446 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); in rzv2h_pmc_writeb()
455 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_set_pfc_mode()
457 /* Set pin to 'Non-use (Hi-Z input protection)' */ in rzg2l_pinctrl_set_pfc_mode()
458 reg = readw(pctrl->base + PM(off)); in rzg2l_pinctrl_set_pfc_mode()
460 writew(reg, pctrl->base + PM(off)); in rzg2l_pinctrl_set_pfc_mode()
462 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); in rzg2l_pinctrl_set_pfc_mode()
465 reg = readb(pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
466 writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
469 reg = readl(pctrl->base + PFC(off)); in rzg2l_pinctrl_set_pfc_mode()
471 writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); in rzg2l_pinctrl_set_pfc_mode()
474 reg = readb(pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
475 writeb(reg | BIT(pin), pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
477 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); in rzg2l_pinctrl_set_pfc_mode()
479 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_set_pfc_mode()
487 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_set_mux()
495 return -EINVAL; in rzg2l_pinctrl_set_mux()
498 return -EINVAL; in rzg2l_pinctrl_set_mux()
500 psel_val = func->data; in rzg2l_pinctrl_set_mux()
501 pins = group->grp.pins; in rzg2l_pinctrl_set_mux()
503 for (i = 0; i < group->grp.npins; i++) { in rzg2l_pinctrl_set_mux()
504 u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; in rzg2l_pinctrl_set_mux()
508 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", in rzg2l_pinctrl_set_mux()
509 RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); in rzg2l_pinctrl_set_mux()
511 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); in rzg2l_pinctrl_set_mux()
527 return -ENOMEM; in rzg2l_map_add_config()
529 map->type = type; in rzg2l_map_add_config()
530 map->data.configs.group_or_pin = group_or_pin; in rzg2l_map_add_config()
531 map->data.configs.configs = cfgs; in rzg2l_map_add_config()
532 map->data.configs.num_configs = num_configs; in rzg2l_map_add_config()
562 num_pinmux = pinmux->length / sizeof(u32); in rzg2l_dt_subnode_to_map()
565 if (ret == -EINVAL) { in rzg2l_dt_subnode_to_map()
568 dev_err(pctrl->dev, "Invalid pins list in DT\n"); in rzg2l_dt_subnode_to_map()
578 dev_err(pctrl->dev, in rzg2l_dt_subnode_to_map()
580 return -EINVAL; in rzg2l_dt_subnode_to_map()
588 dev_err(pctrl->dev, "DT node must contain a config\n"); in rzg2l_dt_subnode_to_map()
589 ret = -ENODEV; in rzg2l_dt_subnode_to_map()
604 ret = -ENOMEM; in rzg2l_dt_subnode_to_map()
624 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); in rzg2l_dt_subnode_to_map()
625 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), in rzg2l_dt_subnode_to_map()
627 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); in rzg2l_dt_subnode_to_map()
629 ret = -ENOMEM; in rzg2l_dt_subnode_to_map()
645 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", in rzg2l_dt_subnode_to_map()
648 ret = -ENOMEM; in rzg2l_dt_subnode_to_map()
652 name = np->name; in rzg2l_dt_subnode_to_map()
665 mutex_lock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
685 mutex_unlock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
692 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); in rzg2l_dt_subnode_to_map()
699 mutex_unlock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
753 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); in rzg2l_dt_node_to_map()
754 ret = -EINVAL; in rzg2l_dt_node_to_map()
769 if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins) in rzg2l_validate_gpio_pin()
770 return -EINVAL; in rzg2l_validate_gpio_pin()
772 data = pctrl->data->port_pin_configs[port]; in rzg2l_validate_gpio_pin()
774 return -EINVAL; in rzg2l_validate_gpio_pin()
782 void __iomem *addr = pctrl->base + offset; in rzg2l_read_pin_config()
784 /* handle _L/_H for 32-bit register read/write */ in rzg2l_read_pin_config()
786 bit -= 4; in rzg2l_read_pin_config()
796 void __iomem *addr = pctrl->base + offset; in rzg2l_rmw_pin_config()
800 /* handle _L/_H for 32-bit register read/write */ in rzg2l_rmw_pin_config()
802 bit -= 4; in rzg2l_rmw_pin_config()
806 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_rmw_pin_config()
809 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_rmw_pin_config()
815 return SD_CH(regs->sd_ch, 0); in rzg2l_caps_to_pwr_reg()
817 return SD_CH(regs->sd_ch, 1); in rzg2l_caps_to_pwr_reg()
819 return ETH_POC(regs->eth_poc, 0); in rzg2l_caps_to_pwr_reg()
821 return ETH_POC(regs->eth_poc, 1); in rzg2l_caps_to_pwr_reg()
825 return -EINVAL; in rzg2l_caps_to_pwr_reg()
830 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_get_power_source()
831 const struct rzg2l_register_offsets *regs = &hwcfg->regs; in rzg2l_get_power_source()
836 return pctrl->settings[pin].power_source; in rzg2l_get_power_source()
842 val = readb(pctrl->base + pwr_reg); in rzg2l_get_power_source()
852 return -EINVAL; in rzg2l_get_power_source()
858 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_set_power_source()
859 const struct rzg2l_register_offsets *regs = &hwcfg->regs; in rzg2l_set_power_source()
864 pctrl->settings[pin].power_source = ps; in rzg2l_set_power_source()
874 return -EINVAL; in rzg2l_set_power_source()
881 return -EINVAL; in rzg2l_set_power_source()
888 writeb(val, pctrl->base + pwr_reg); in rzg2l_set_power_source()
889 pctrl->settings[pin].power_source = ps; in rzg2l_set_power_source()
925 return hwcfg->iolh_groupa_ua[val]; in rzg2l_iolh_val_to_ua()
928 return hwcfg->iolh_groupb_ua[val]; in rzg2l_iolh_val_to_ua()
931 return hwcfg->iolh_groupc_ua[val]; in rzg2l_iolh_val_to_ua()
944 array = &hwcfg->iolh_groupa_ua[ps_index]; in rzg2l_iolh_ua_to_val()
947 array = &hwcfg->iolh_groupb_ua[ps_index]; in rzg2l_iolh_ua_to_val()
950 array = &hwcfg->iolh_groupc_ua[ps_index]; in rzg2l_iolh_ua_to_val()
953 return -EINVAL; in rzg2l_iolh_ua_to_val()
960 return -EINVAL; in rzg2l_iolh_ua_to_val()
967 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_ds_is_supported()
972 array = hwcfg->iolh_groupa_ua; in rzg2l_ds_is_supported()
975 array = hwcfg->iolh_groupb_ua; in rzg2l_ds_is_supported()
978 array = hwcfg->iolh_groupc_ua; in rzg2l_ds_is_supported()
997 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; in rzg2l_pin_to_oen_bit()
1001 if (pin > pctrl->data->hwcfg->oen_max_pin) in rzg2l_pin_to_oen_bit()
1002 return -EINVAL; in rzg2l_pin_to_oen_bit()
1013 return -EINVAL; in rzg2l_pin_to_oen_bit()
1024 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); in rzg2l_read_oen()
1037 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_write_oen()
1038 val = readb(pctrl->base + ETH_MODE); in rzg2l_write_oen()
1043 writeb(val, pctrl->base + ETH_MODE); in rzg2l_write_oen()
1044 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_write_oen()
1051 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; in rzg3s_pin_to_oen_bit()
1055 return -EINVAL; in rzg3s_pin_to_oen_bit()
1059 if (pin > pctrl->data->hwcfg->oen_max_pin) in rzg3s_pin_to_oen_bit()
1060 return -EINVAL; in rzg3s_pin_to_oen_bit()
1063 if (port == pctrl->data->hwcfg->oen_max_port) in rzg3s_pin_to_oen_bit()
1077 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); in rzg3s_oen_read()
1090 spin_lock_irqsave(&pctrl->lock, flags); in rzg3s_oen_write()
1091 val = readb(pctrl->base + ETH_MODE); in rzg3s_oen_write()
1096 writeb(val, pctrl->base + ETH_MODE); in rzg3s_oen_write()
1097 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg3s_oen_write()
1115 return -EINVAL; in rzg2l_hw_to_bias_param()
1131 return -EINVAL; in rzg2l_bias_param_to_hw()
1148 return -EINVAL; in rzv2h_hw_to_bias_param()
1164 return -EINVAL; in rzv2h_bias_param_to_hw()
1172 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin]; in rzv2h_pin_to_oen_bit()
1176 if (!strcmp(pin_desc->name, pin_names[i])) in rzv2h_pin_to_oen_bit()
1190 return !(readb(pctrl->base + PFC_OEN) & BIT(bit)); in rzv2h_oen_read()
1195 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzv2h_oen_write()
1196 const struct rzg2l_register_offsets *regs = &hwcfg->regs; in rzv2h_oen_write()
1202 spin_lock_irqsave(&pctrl->lock, flags); in rzv2h_oen_write()
1203 val = readb(pctrl->base + PFC_OEN); in rzv2h_oen_write()
1209 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_oen_write()
1210 writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); in rzv2h_oen_write()
1211 writeb(val, pctrl->base + PFC_OEN); in rzv2h_oen_write()
1212 writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); in rzv2h_oen_write()
1213 spin_unlock_irqrestore(&pctrl->lock, flags); in rzv2h_oen_write()
1223 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_pinconf_get()
1224 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzg2l_pinctrl_pinconf_get()
1226 u64 *pin_data = pin->drv_data; in rzg2l_pinctrl_pinconf_get()
1234 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1244 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1250 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1253 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1258 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1259 if (!pctrl->data->oen_read) in rzg2l_pinctrl_pinconf_get()
1260 return -EOPNOTSUPP; in rzg2l_pinctrl_pinconf_get()
1261 arg = pctrl->data->oen_read(pctrl, _pin); in rzg2l_pinctrl_pinconf_get()
1263 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1275 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1284 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1287 ret = pctrl->data->hw_to_bias_param(arg); in rzg2l_pinctrl_pinconf_get()
1292 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1300 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) in rzg2l_pinctrl_pinconf_get()
1301 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1308 arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000; in rzg2l_pinctrl_pinconf_get()
1317 !hwcfg->drive_strength_ua) in rzg2l_pinctrl_pinconf_get()
1318 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1332 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) in rzg2l_pinctrl_pinconf_get()
1333 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1336 arg = hwcfg->iolh_groupb_oi[index]; in rzg2l_pinctrl_pinconf_get()
1342 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1348 return -ENOTSUPP; in rzg2l_pinctrl_pinconf_get()
1362 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzg2l_pinctrl_pinconf_set()
1363 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_pinconf_set()
1364 struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; in rzg2l_pinctrl_pinconf_set()
1365 u64 *pin_data = pin->drv_data; in rzg2l_pinctrl_pinconf_set()
1373 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1383 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1393 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1400 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1401 if (!pctrl->data->oen_write) in rzg2l_pinctrl_pinconf_set()
1402 return -EOPNOTSUPP; in rzg2l_pinctrl_pinconf_set()
1403 ret = pctrl->data->oen_write(pctrl, _pin, !!arg); in rzg2l_pinctrl_pinconf_set()
1414 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1423 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1425 ret = pctrl->data->bias_param_to_hw(param); in rzg2l_pinctrl_pinconf_set()
1433 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) in rzg2l_pinctrl_pinconf_set()
1434 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1438 if (arg == (hwcfg->iolh_groupa_ua[index] / 1000)) in rzg2l_pinctrl_pinconf_set()
1442 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1449 !hwcfg->drive_strength_ua) in rzg2l_pinctrl_pinconf_set()
1450 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1456 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) in rzg2l_pinctrl_pinconf_set()
1457 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1459 for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) { in rzg2l_pinctrl_pinconf_set()
1460 if (arg == hwcfg->iolh_groupb_oi[index]) in rzg2l_pinctrl_pinconf_set()
1463 if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi)) in rzg2l_pinctrl_pinconf_set()
1464 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1471 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1474 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1479 return -EOPNOTSUPP; in rzg2l_pinctrl_pinconf_set()
1484 if (settings.power_source != pctrl->settings[_pin].power_source) { in rzg2l_pinctrl_pinconf_set()
1487 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1496 if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) { in rzg2l_pinctrl_pinconf_set()
1504 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1513 pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua; in rzg2l_pinctrl_pinconf_set()
1561 return -EOPNOTSUPP; in rzg2l_pinctrl_pinconf_group_get()
1597 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_request()
1598 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_request()
1614 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_request()
1617 reg8 = readb(pctrl->base + PMC(off)); in rzg2l_gpio_request()
1619 pctrl->data->pmc_writeb(pctrl, reg8, PMC(off)); in rzg2l_gpio_request()
1621 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_request()
1629 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_set_direction()
1630 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_set_direction()
1636 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_set_direction()
1638 reg16 = readw(pctrl->base + PM(off)); in rzg2l_gpio_set_direction()
1642 writew(reg16, pctrl->base + PM(off)); in rzg2l_gpio_set_direction()
1644 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_set_direction()
1650 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_get_direction()
1651 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_get_direction()
1655 if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) { in rzg2l_gpio_get_direction()
1658 reg16 = readw(pctrl->base + PM(off)); in rzg2l_gpio_get_direction()
1681 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_set()
1682 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_set()
1688 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_set()
1690 reg8 = readb(pctrl->base + P(off)); in rzg2l_gpio_set()
1693 writeb(reg8 | BIT(bit), pctrl->base + P(off)); in rzg2l_gpio_set()
1695 writeb(reg8 & ~BIT(bit), pctrl->base + P(off)); in rzg2l_gpio_set()
1697 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_set()
1714 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_get()
1715 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_get()
1720 reg16 = readw(pctrl->base + PM(off)); in rzg2l_gpio_get()
1724 return !!(readb(pctrl->base + PIN(off)) & BIT(bit)); in rzg2l_gpio_get()
1726 return !!(readb(pctrl->base + P(off)) & BIT(bit)); in rzg2l_gpio_get()
1728 return -EINVAL; in rzg2l_gpio_get()
1737 virq = irq_find_mapping(chip->irq.domain, offset); in rzg2l_gpio_free()
1873 /* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */
2213 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; in rzg2l_gpio_get_gpioint()
2214 const struct rzg2l_pinctrl_data *data = pctrl->data; in rzg2l_gpio_get_gpioint()
2215 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_get_gpioint()
2221 return -EINVAL; in rzg2l_gpio_get_gpioint()
2226 if (port >= data->n_ports || in rzg2l_gpio_get_gpioint()
2227 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port]))) in rzg2l_gpio_get_gpioint()
2228 return -EINVAL; in rzg2l_gpio_get_gpioint()
2232 gpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i])); in rzg2l_gpio_get_gpioint()
2240 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; in rzg2l_gpio_irq_endisable()
2241 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_irq_endisable()
2247 addr = pctrl->base + ISEL(off); in rzg2l_gpio_irq_endisable()
2249 bit -= 4; in rzg2l_gpio_irq_endisable()
2253 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_irq_endisable()
2258 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_irq_endisable()
2293 seq_printf(p, dev_name(gc->parent)); in rzg2l_gpio_irq_print_chip()
2303 if (!data->parent_data) in rzg2l_gpio_irq_set_wake()
2304 return -EOPNOTSUPP; in rzg2l_gpio_irq_set_wake()
2311 atomic_inc(&pctrl->wakeup_path); in rzg2l_gpio_irq_set_wake()
2313 atomic_dec(&pctrl->wakeup_path); in rzg2l_gpio_irq_set_wake()
2319 .name = "rzg2l-gpio",
2336 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_interrupt_input_mode()
2337 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_interrupt_input_mode()
2343 reg8 = readb(pctrl->base + PMC(off)); in rzg2l_gpio_interrupt_input_mode()
2372 spin_lock_irqsave(&pctrl->bitmap_lock, flags); in rzg2l_gpio_child_to_parent_hwirq()
2373 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); in rzg2l_gpio_child_to_parent_hwirq()
2374 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); in rzg2l_gpio_child_to_parent_hwirq()
2376 ret = -ENOSPC; in rzg2l_gpio_child_to_parent_hwirq()
2381 pctrl->hwirq[irq] = child; in rzg2l_gpio_child_to_parent_hwirq()
2399 struct irq_fwspec *fwspec = &gfwspec->fwspec; in rzg2l_gpio_populate_parent_fwspec()
2401 fwspec->fwnode = chip->irq.parent_domain->fwnode; in rzg2l_gpio_populate_parent_fwspec()
2402 fwspec->param_count = 2; in rzg2l_gpio_populate_parent_fwspec()
2403 fwspec->param[0] = parent_hwirq; in rzg2l_gpio_populate_parent_fwspec()
2404 fwspec->param[1] = parent_type; in rzg2l_gpio_populate_parent_fwspec()
2411 struct irq_domain *domain = pctrl->gpio_chip.irq.domain; in rzg2l_gpio_irq_restore()
2419 if (!pctrl->hwirq[i]) in rzg2l_gpio_irq_restore()
2422 virq = irq_find_mapping(domain, pctrl->hwirq[i]); in rzg2l_gpio_irq_restore()
2424 dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n", in rzg2l_gpio_irq_restore()
2425 pctrl->hwirq[i]); in rzg2l_gpio_irq_restore()
2431 dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq); in rzg2l_gpio_irq_restore()
2439 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_irq_restore()
2443 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_irq_restore()
2446 dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq); in rzg2l_gpio_irq_restore()
2464 if (pctrl->hwirq[i] == hwirq) { in rzg2l_gpio_irq_domain_free()
2467 spin_lock_irqsave(&pctrl->bitmap_lock, flags); in rzg2l_gpio_irq_domain_free()
2468 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); in rzg2l_gpio_irq_domain_free()
2469 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); in rzg2l_gpio_irq_domain_free()
2470 pctrl->hwirq[i] = 0; in rzg2l_gpio_irq_domain_free()
2483 struct gpio_chip *chip = &pctrl->gpio_chip; in rzg2l_init_irq_valid_mask()
2487 for (offset = 0; offset < chip->ngpio; offset++) { in rzg2l_init_irq_valid_mask()
2493 if (port >= pctrl->data->n_ports || in rzg2l_init_irq_valid_mask()
2495 pctrl->data->port_pin_configs[port]))) in rzg2l_init_irq_valid_mask()
2502 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; in rzg2l_pinctrl_reg_cache_alloc()
2505 cache = devm_kzalloc(pctrl->dev, sizeof(*cache), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2507 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2509 dedicated_cache = devm_kzalloc(pctrl->dev, sizeof(*dedicated_cache), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2511 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2513 cache->p = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->p), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2514 if (!cache->p) in rzg2l_pinctrl_reg_cache_alloc()
2515 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2517 cache->pm = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pm), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2518 if (!cache->pm) in rzg2l_pinctrl_reg_cache_alloc()
2519 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2521 cache->pmc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pmc), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2522 if (!cache->pmc) in rzg2l_pinctrl_reg_cache_alloc()
2523 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2525 cache->pfc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pfc), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2526 if (!cache->pfc) in rzg2l_pinctrl_reg_cache_alloc()
2527 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2530 u32 n_dedicated_pins = pctrl->data->n_dedicated_pins; in rzg2l_pinctrl_reg_cache_alloc()
2532 cache->iolh[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->iolh[i]), in rzg2l_pinctrl_reg_cache_alloc()
2534 if (!cache->iolh[i]) in rzg2l_pinctrl_reg_cache_alloc()
2535 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2537 cache->ien[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->ien[i]), in rzg2l_pinctrl_reg_cache_alloc()
2539 if (!cache->ien[i]) in rzg2l_pinctrl_reg_cache_alloc()
2540 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2543 dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, in rzg2l_pinctrl_reg_cache_alloc()
2544 sizeof(*dedicated_cache->iolh[i]), in rzg2l_pinctrl_reg_cache_alloc()
2546 if (!dedicated_cache->iolh[i]) in rzg2l_pinctrl_reg_cache_alloc()
2547 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2549 dedicated_cache->ien[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, in rzg2l_pinctrl_reg_cache_alloc()
2550 sizeof(*dedicated_cache->ien[i]), in rzg2l_pinctrl_reg_cache_alloc()
2552 if (!dedicated_cache->ien[i]) in rzg2l_pinctrl_reg_cache_alloc()
2553 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2556 pctrl->cache = cache; in rzg2l_pinctrl_reg_cache_alloc()
2557 pctrl->dedicated_cache = dedicated_cache; in rzg2l_pinctrl_reg_cache_alloc()
2564 struct device_node *np = pctrl->dev->of_node; in rzg2l_gpio_register()
2565 struct gpio_chip *chip = &pctrl->gpio_chip; in rzg2l_gpio_register()
2566 const char *name = dev_name(pctrl->dev); in rzg2l_gpio_register()
2575 return -ENXIO; in rzg2l_gpio_register()
2580 return -EPROBE_DEFER; in rzg2l_gpio_register()
2582 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); in rzg2l_gpio_register()
2584 return dev_err_probe(pctrl->dev, ret, "Unable to parse gpio-ranges\n"); in rzg2l_gpio_register()
2587 of_args.args[2] != pctrl->data->n_port_pins) in rzg2l_gpio_register()
2588 return dev_err_probe(pctrl->dev, -EINVAL, in rzg2l_gpio_register()
2589 "gpio-ranges does not match selected SOC\n"); in rzg2l_gpio_register()
2591 chip->names = pctrl->data->port_pins; in rzg2l_gpio_register()
2592 chip->request = rzg2l_gpio_request; in rzg2l_gpio_register()
2593 chip->free = rzg2l_gpio_free; in rzg2l_gpio_register()
2594 chip->get_direction = rzg2l_gpio_get_direction; in rzg2l_gpio_register()
2595 chip->direction_input = rzg2l_gpio_direction_input; in rzg2l_gpio_register()
2596 chip->direction_output = rzg2l_gpio_direction_output; in rzg2l_gpio_register()
2597 chip->get = rzg2l_gpio_get; in rzg2l_gpio_register()
2598 chip->set = rzg2l_gpio_set; in rzg2l_gpio_register()
2599 chip->label = name; in rzg2l_gpio_register()
2600 chip->parent = pctrl->dev; in rzg2l_gpio_register()
2601 chip->owner = THIS_MODULE; in rzg2l_gpio_register()
2602 chip->base = -1; in rzg2l_gpio_register()
2603 chip->ngpio = of_args.args[2]; in rzg2l_gpio_register()
2605 girq = &chip->irq; in rzg2l_gpio_register()
2607 girq->fwnode = dev_fwnode(pctrl->dev); in rzg2l_gpio_register()
2608 girq->parent_domain = parent_domain; in rzg2l_gpio_register()
2609 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; in rzg2l_gpio_register()
2610 girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec; in rzg2l_gpio_register()
2611 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; in rzg2l_gpio_register()
2612 girq->init_valid_mask = rzg2l_init_irq_valid_mask; in rzg2l_gpio_register()
2614 pctrl->gpio_range.id = 0; in rzg2l_gpio_register()
2615 pctrl->gpio_range.pin_base = 0; in rzg2l_gpio_register()
2616 pctrl->gpio_range.base = 0; in rzg2l_gpio_register()
2617 pctrl->gpio_range.npins = chip->ngpio; in rzg2l_gpio_register()
2618 pctrl->gpio_range.name = chip->label; in rzg2l_gpio_register()
2619 pctrl->gpio_range.gc = chip; in rzg2l_gpio_register()
2620 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); in rzg2l_gpio_register()
2622 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO controller\n"); in rzg2l_gpio_register()
2624 dev_dbg(pctrl->dev, "Registered gpio controller\n"); in rzg2l_gpio_register()
2631 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_register()
2637 pctrl->desc.name = DRV_NAME; in rzg2l_pinctrl_register()
2638 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; in rzg2l_pinctrl_register()
2639 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; in rzg2l_pinctrl_register()
2640 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; in rzg2l_pinctrl_register()
2641 pctrl->desc.confops = &rzg2l_pinctrl_confops; in rzg2l_pinctrl_register()
2642 pctrl->desc.owner = THIS_MODULE; in rzg2l_pinctrl_register()
2643 if (pctrl->data->num_custom_params) { in rzg2l_pinctrl_register()
2644 pctrl->desc.num_custom_params = pctrl->data->num_custom_params; in rzg2l_pinctrl_register()
2645 pctrl->desc.custom_params = pctrl->data->custom_params; in rzg2l_pinctrl_register()
2647 pctrl->desc.custom_conf_items = pctrl->data->custom_conf_items; in rzg2l_pinctrl_register()
2651 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); in rzg2l_pinctrl_register()
2653 return -ENOMEM; in rzg2l_pinctrl_register()
2655 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, in rzg2l_pinctrl_register()
2658 return -ENOMEM; in rzg2l_pinctrl_register()
2660 pctrl->pins = pins; in rzg2l_pinctrl_register()
2661 pctrl->desc.pins = pins; in rzg2l_pinctrl_register()
2663 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { in rzg2l_pinctrl_register()
2665 pins[i].name = pctrl->data->port_pins[i]; in rzg2l_pinctrl_register()
2668 pin_data[i] = pctrl->data->port_pin_configs[j]; in rzg2l_pinctrl_register()
2677 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { in rzg2l_pinctrl_register()
2678 unsigned int index = pctrl->data->n_port_pins + i; in rzg2l_pinctrl_register()
2681 pins[index].name = pctrl->data->dedicated_pins[i].name; in rzg2l_pinctrl_register()
2682 pin_data[index] = pctrl->data->dedicated_pins[i].config; in rzg2l_pinctrl_register()
2686 pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings), in rzg2l_pinctrl_register()
2688 if (!pctrl->settings) in rzg2l_pinctrl_register()
2689 return -ENOMEM; in rzg2l_pinctrl_register()
2691 for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) { in rzg2l_pinctrl_register()
2693 pctrl->settings[i].power_source = 3300; in rzg2l_pinctrl_register()
2698 pctrl->settings[i].power_source = ret; in rzg2l_pinctrl_register()
2706 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, in rzg2l_pinctrl_register()
2707 &pctrl->pctl); in rzg2l_pinctrl_register()
2709 return dev_err_probe(pctrl->dev, ret, "pinctrl registration failed\n"); in rzg2l_pinctrl_register()
2711 ret = pinctrl_enable(pctrl->pctl); in rzg2l_pinctrl_register()
2713 dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n"); in rzg2l_pinctrl_register()
2717 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO chip\n"); in rzg2l_pinctrl_register()
2739 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in rzg2l_pinctrl_probe()
2741 return -ENOMEM; in rzg2l_pinctrl_probe()
2743 pctrl->dev = &pdev->dev; in rzg2l_pinctrl_probe()
2745 pctrl->data = of_device_get_match_data(&pdev->dev); in rzg2l_pinctrl_probe()
2746 if (!pctrl->data) in rzg2l_pinctrl_probe()
2747 return -EINVAL; in rzg2l_pinctrl_probe()
2749 pctrl->base = devm_platform_ioremap_resource(pdev, 0); in rzg2l_pinctrl_probe()
2750 if (IS_ERR(pctrl->base)) in rzg2l_pinctrl_probe()
2751 return PTR_ERR(pctrl->base); in rzg2l_pinctrl_probe()
2753 pctrl->clk = devm_clk_get_enabled(pctrl->dev, NULL); in rzg2l_pinctrl_probe()
2754 if (IS_ERR(pctrl->clk)) { in rzg2l_pinctrl_probe()
2755 return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->clk), in rzg2l_pinctrl_probe()
2759 spin_lock_init(&pctrl->lock); in rzg2l_pinctrl_probe()
2760 spin_lock_init(&pctrl->bitmap_lock); in rzg2l_pinctrl_probe()
2761 mutex_init(&pctrl->mutex); in rzg2l_pinctrl_probe()
2762 atomic_set(&pctrl->wakeup_path, 0); in rzg2l_pinctrl_probe()
2770 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); in rzg2l_pinctrl_probe()
2776 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; in rzg2l_pinctrl_pm_setup_regs()
2777 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_pm_setup_regs()
2785 cfg = pctrl->data->port_pin_configs[port]; in rzg2l_pinctrl_pm_setup_regs()
2794 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); in rzg2l_pinctrl_pm_setup_regs()
2800 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]); in rzg2l_pinctrl_pm_setup_regs()
2802 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), in rzg2l_pinctrl_pm_setup_regs()
2803 cache->iolh[0][port]); in rzg2l_pinctrl_pm_setup_regs()
2805 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4, in rzg2l_pinctrl_pm_setup_regs()
2806 cache->iolh[1][port]); in rzg2l_pinctrl_pm_setup_regs()
2810 RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]); in rzg2l_pinctrl_pm_setup_regs()
2811 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]); in rzg2l_pinctrl_pm_setup_regs()
2814 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), in rzg2l_pinctrl_pm_setup_regs()
2815 cache->ien[0][port]); in rzg2l_pinctrl_pm_setup_regs()
2817 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4, in rzg2l_pinctrl_pm_setup_regs()
2818 cache->ien[1][port]); in rzg2l_pinctrl_pm_setup_regs()
2826 struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache; in rzg2l_pinctrl_pm_setup_dedicated_regs()
2831 * Make sure entries in pctrl->data->n_dedicated_pins[] having the same in rzg2l_pinctrl_pm_setup_dedicated_regs()
2834 for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { in rzg2l_pinctrl_pm_setup_dedicated_regs()
2840 cfg = pctrl->data->dedicated_pins[i].config; in rzg2l_pinctrl_pm_setup_dedicated_regs()
2842 if (i + 1 < pctrl->data->n_dedicated_pins) { in rzg2l_pinctrl_pm_setup_dedicated_regs()
2843 next_cfg = pctrl->data->dedicated_pins[i + 1].config; in rzg2l_pinctrl_pm_setup_dedicated_regs()
2859 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), in rzg2l_pinctrl_pm_setup_dedicated_regs()
2860 cache->iolh[0][i]); in rzg2l_pinctrl_pm_setup_dedicated_regs()
2863 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), in rzg2l_pinctrl_pm_setup_dedicated_regs()
2864 cache->ien[0][i]); in rzg2l_pinctrl_pm_setup_dedicated_regs()
2870 pctrl->base + IOLH(off) + 4, in rzg2l_pinctrl_pm_setup_dedicated_regs()
2871 cache->iolh[1][i]); in rzg2l_pinctrl_pm_setup_dedicated_regs()
2875 pctrl->base + IEN(off) + 4, in rzg2l_pinctrl_pm_setup_dedicated_regs()
2876 cache->ien[1][i]); in rzg2l_pinctrl_pm_setup_dedicated_regs()
2885 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; in rzg2l_pinctrl_pm_setup_pfc()
2888 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_pm_setup_pfc()
2889 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); in rzg2l_pinctrl_pm_setup_pfc()
2900 cfg = pctrl->data->port_pin_configs[port]; in rzg2l_pinctrl_pm_setup_pfc()
2905 pm = readw(pctrl->base + PM(off)); in rzg2l_pinctrl_pm_setup_pfc()
2907 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_pm_setup_pfc()
2910 if (!(cache->pmc[port] & BIT(pin))) in rzg2l_pinctrl_pm_setup_pfc()
2913 /* Set pin to 'Non-use (Hi-Z input protection)' */ in rzg2l_pinctrl_pm_setup_pfc()
2915 writew(pm, pctrl->base + PM(off)); in rzg2l_pinctrl_pm_setup_pfc()
2919 writeb(pmc, pctrl->base + PMC(off)); in rzg2l_pinctrl_pm_setup_pfc()
2923 pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4))); in rzg2l_pinctrl_pm_setup_pfc()
2924 writel(pfc, pctrl->base + PFC(off)); in rzg2l_pinctrl_pm_setup_pfc()
2928 writeb(pmc, pctrl->base + PMC(off)); in rzg2l_pinctrl_pm_setup_pfc()
2932 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); in rzg2l_pinctrl_pm_setup_pfc()
2933 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_pm_setup_pfc()
2939 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_suspend_noirq()
2940 const struct rzg2l_register_offsets *regs = &hwcfg->regs; in rzg2l_pinctrl_suspend_noirq()
2941 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_suspend_noirq()
2947 if (regs->sd_ch) in rzg2l_pinctrl_suspend_noirq()
2948 cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); in rzg2l_pinctrl_suspend_noirq()
2949 if (regs->eth_poc) in rzg2l_pinctrl_suspend_noirq()
2950 cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); in rzg2l_pinctrl_suspend_noirq()
2953 cache->qspi = readb(pctrl->base + QSPI); in rzg2l_pinctrl_suspend_noirq()
2954 cache->eth_mode = readb(pctrl->base + ETH_MODE); in rzg2l_pinctrl_suspend_noirq()
2956 if (!atomic_read(&pctrl->wakeup_path)) in rzg2l_pinctrl_suspend_noirq()
2957 clk_disable_unprepare(pctrl->clk); in rzg2l_pinctrl_suspend_noirq()
2967 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_resume_noirq()
2968 const struct rzg2l_register_offsets *regs = &hwcfg->regs; in rzg2l_pinctrl_resume_noirq()
2969 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_resume_noirq()
2972 if (!atomic_read(&pctrl->wakeup_path)) { in rzg2l_pinctrl_resume_noirq()
2973 ret = clk_prepare_enable(pctrl->clk); in rzg2l_pinctrl_resume_noirq()
2978 writeb(cache->qspi, pctrl->base + QSPI); in rzg2l_pinctrl_resume_noirq()
2979 writeb(cache->eth_mode, pctrl->base + ETH_MODE); in rzg2l_pinctrl_resume_noirq()
2981 if (regs->sd_ch) in rzg2l_pinctrl_resume_noirq()
2982 writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); in rzg2l_pinctrl_resume_noirq()
2983 if (regs->eth_poc) in rzg2l_pinctrl_resume_noirq()
2984 writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); in rzg2l_pinctrl_resume_noirq()
2997 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; in rzg2l_pwpr_pfc_lock_unlock()
3000 /* Set the PWPR register to be write-protected */ in rzg2l_pwpr_pfc_lock_unlock()
3001 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ in rzg2l_pwpr_pfc_lock_unlock()
3002 writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ in rzg2l_pwpr_pfc_lock_unlock()
3005 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ in rzg2l_pwpr_pfc_lock_unlock()
3006 writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ in rzg2l_pwpr_pfc_lock_unlock()
3012 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; in rzv2h_pwpr_pfc_lock_unlock()
3016 /* Set the PWPR register to be write-protected */ in rzv2h_pwpr_pfc_lock_unlock()
3017 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3018 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3021 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3022 writeb(PWPR_REGWE_A | pwpr, pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3156 .compatible = "renesas,r9a07g043-pinctrl",
3160 .compatible = "renesas,r9a07g044-pinctrl",
3164 .compatible = "renesas,r9a08g045-pinctrl",
3168 .compatible = "renesas,r9a09g057-pinctrl",
3193 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");