Lines Matching full:pctrl
289 void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
290 void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
291 u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);
292 int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen);
361 static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, in rzg2l_pinctrl_get_variable_pin_cfg() argument
368 for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) { in rzg2l_pinctrl_get_variable_pin_cfg()
369 u64 cfg = pctrl->data->variable_pin_cfg[i]; in rzg2l_pinctrl_get_variable_pin_cfg()
433 static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset) in rzg2l_pmc_writeb() argument
435 writeb(val, pctrl->base + offset); in rzg2l_pmc_writeb()
438 static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset) in rzv2h_pmc_writeb() argument
440 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; in rzv2h_pmc_writeb()
443 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_pmc_writeb()
444 writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr); in rzv2h_pmc_writeb()
445 writeb(val, pctrl->base + offset); in rzv2h_pmc_writeb()
446 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); in rzv2h_pmc_writeb()
449 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, in rzg2l_pinctrl_set_pfc_mode() argument
455 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_set_pfc_mode()
458 reg = readw(pctrl->base + PM(off)); in rzg2l_pinctrl_set_pfc_mode()
460 writew(reg, pctrl->base + PM(off)); in rzg2l_pinctrl_set_pfc_mode()
462 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); in rzg2l_pinctrl_set_pfc_mode()
465 reg = readb(pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
466 writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
469 reg = readl(pctrl->base + PFC(off)); in rzg2l_pinctrl_set_pfc_mode()
471 writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); in rzg2l_pinctrl_set_pfc_mode()
474 reg = readb(pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
475 writeb(reg | BIT(pin), pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
477 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); in rzg2l_pinctrl_set_pfc_mode()
479 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_set_pfc_mode()
486 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_pinctrl_set_mux() local
487 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_set_mux()
504 u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; in rzg2l_pinctrl_set_mux()
508 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", in rzg2l_pinctrl_set_mux()
511 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); in rzg2l_pinctrl_set_mux()
544 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_dt_subnode_to_map() local
568 dev_err(pctrl->dev, "Invalid pins list in DT\n"); in rzg2l_dt_subnode_to_map()
578 dev_err(pctrl->dev, in rzg2l_dt_subnode_to_map()
588 dev_err(pctrl->dev, "DT node must contain a config\n"); in rzg2l_dt_subnode_to_map()
624 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); in rzg2l_dt_subnode_to_map()
625 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), in rzg2l_dt_subnode_to_map()
627 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); in rzg2l_dt_subnode_to_map()
645 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", in rzg2l_dt_subnode_to_map()
665 mutex_lock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
685 mutex_unlock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
692 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); in rzg2l_dt_subnode_to_map()
699 mutex_unlock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
728 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_dt_node_to_map() local
753 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); in rzg2l_dt_node_to_map()
762 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, in rzg2l_validate_gpio_pin() argument
769 if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins) in rzg2l_validate_gpio_pin()
772 data = pctrl->data->port_pin_configs[port]; in rzg2l_validate_gpio_pin()
779 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, in rzg2l_read_pin_config() argument
782 void __iomem *addr = pctrl->base + offset; in rzg2l_read_pin_config()
793 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, in rzg2l_rmw_pin_config() argument
796 void __iomem *addr = pctrl->base + offset; in rzg2l_rmw_pin_config()
806 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_rmw_pin_config()
809 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_rmw_pin_config()
828 static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps) in rzg2l_get_power_source() argument
830 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_get_power_source()
836 return pctrl->settings[pin].power_source; in rzg2l_get_power_source()
842 val = readb(pctrl->base + pwr_reg); in rzg2l_get_power_source()
856 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) in rzg2l_set_power_source() argument
858 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_set_power_source()
864 pctrl->settings[pin].power_source = ps; in rzg2l_set_power_source()
888 writeb(val, pctrl->base + pwr_reg); in rzg2l_set_power_source()
889 pctrl->settings[pin].power_source = ps; in rzg2l_set_power_source()
963 static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, in rzg2l_ds_is_supported() argument
967 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_ds_is_supported()
995 static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) in rzg2l_pin_to_oen_bit() argument
997 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; in rzg2l_pin_to_oen_bit()
1001 if (pin > pctrl->data->hwcfg->oen_max_pin) in rzg2l_pin_to_oen_bit()
1016 static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) in rzg2l_read_oen() argument
1020 bit = rzg2l_pin_to_oen_bit(pctrl, _pin); in rzg2l_read_oen()
1024 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); in rzg2l_read_oen()
1027 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) in rzg2l_write_oen() argument
1033 bit = rzg2l_pin_to_oen_bit(pctrl, _pin); in rzg2l_write_oen()
1037 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_write_oen()
1038 val = readb(pctrl->base + ETH_MODE); in rzg2l_write_oen()
1043 writeb(val, pctrl->base + ETH_MODE); in rzg2l_write_oen()
1044 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_write_oen()
1049 static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) in rzg3s_pin_to_oen_bit() argument
1051 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; in rzg3s_pin_to_oen_bit()
1059 if (pin > pctrl->data->hwcfg->oen_max_pin) in rzg3s_pin_to_oen_bit()
1063 if (port == pctrl->data->hwcfg->oen_max_port) in rzg3s_pin_to_oen_bit()
1069 static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) in rzg3s_oen_read() argument
1073 bit = rzg3s_pin_to_oen_bit(pctrl, _pin); in rzg3s_oen_read()
1077 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); in rzg3s_oen_read()
1080 static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) in rzg3s_oen_write() argument
1086 bit = rzg3s_pin_to_oen_bit(pctrl, _pin); in rzg3s_oen_write()
1090 spin_lock_irqsave(&pctrl->lock, flags); in rzg3s_oen_write()
1091 val = readb(pctrl->base + ETH_MODE); in rzg3s_oen_write()
1096 writeb(val, pctrl->base + ETH_MODE); in rzg3s_oen_write()
1097 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg3s_oen_write()
1167 static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) in rzv2h_pin_to_oen_bit() argument
1172 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin]; in rzv2h_pin_to_oen_bit()
1184 static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) in rzv2h_oen_read() argument
1188 bit = rzv2h_pin_to_oen_bit(pctrl, _pin); in rzv2h_oen_read()
1190 return !(readb(pctrl->base + PFC_OEN) & BIT(bit)); in rzv2h_oen_read()
1193 static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) in rzv2h_oen_write() argument
1195 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzv2h_oen_write()
1201 bit = rzv2h_pin_to_oen_bit(pctrl, _pin); in rzv2h_oen_write()
1202 spin_lock_irqsave(&pctrl->lock, flags); in rzv2h_oen_write()
1203 val = readb(pctrl->base + PFC_OEN); in rzv2h_oen_write()
1209 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_oen_write()
1210 writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); in rzv2h_oen_write()
1211 writeb(val, pctrl->base + PFC_OEN); in rzv2h_oen_write()
1212 writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); in rzv2h_oen_write()
1213 spin_unlock_irqrestore(&pctrl->lock, flags); in rzv2h_oen_write()
1222 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_pinctrl_pinconf_get() local
1223 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_pinconf_get()
1224 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzg2l_pinctrl_pinconf_get()
1243 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) in rzg2l_pinctrl_pinconf_get()
1251 arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK); in rzg2l_pinctrl_pinconf_get()
1259 if (!pctrl->data->oen_read) in rzg2l_pinctrl_pinconf_get()
1261 arg = pctrl->data->oen_read(pctrl, _pin); in rzg2l_pinctrl_pinconf_get()
1267 ret = rzg2l_get_power_source(pctrl, _pin, cfg); in rzg2l_pinctrl_pinconf_get()
1277 arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK); in rzg2l_pinctrl_pinconf_get()
1286 arg = rzg2l_read_pin_config(pctrl, PUPD(off), bit, PUPD_MASK); in rzg2l_pinctrl_pinconf_get()
1287 ret = pctrl->data->hw_to_bias_param(arg); in rzg2l_pinctrl_pinconf_get()
1303 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); in rzg2l_pinctrl_pinconf_get()
1320 ret = rzg2l_get_power_source(pctrl, _pin, cfg); in rzg2l_pinctrl_pinconf_get()
1324 val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); in rzg2l_pinctrl_pinconf_get()
1335 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); in rzg2l_pinctrl_pinconf_get()
1344 arg = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); in rzg2l_pinctrl_pinconf_get()
1361 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_pinctrl_pinconf_set() local
1362 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzg2l_pinctrl_pinconf_set()
1363 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_pinconf_set()
1364 struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; in rzg2l_pinctrl_pinconf_set()
1382 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) in rzg2l_pinctrl_pinconf_set()
1395 rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg); in rzg2l_pinctrl_pinconf_set()
1401 if (!pctrl->data->oen_write) in rzg2l_pinctrl_pinconf_set()
1403 ret = pctrl->data->oen_write(pctrl, _pin, !!arg); in rzg2l_pinctrl_pinconf_set()
1416 rzg2l_rmw_pin_config(pctrl, SR(off), bit, SR_MASK, arg); in rzg2l_pinctrl_pinconf_set()
1425 ret = pctrl->data->bias_param_to_hw(param); in rzg2l_pinctrl_pinconf_set()
1429 rzg2l_rmw_pin_config(pctrl, PUPD(off), bit, PUPD_MASK, ret); in rzg2l_pinctrl_pinconf_set()
1444 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); in rzg2l_pinctrl_pinconf_set()
1466 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); in rzg2l_pinctrl_pinconf_set()
1475 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, arg); in rzg2l_pinctrl_pinconf_set()
1484 if (settings.power_source != pctrl->settings[_pin].power_source) { in rzg2l_pinctrl_pinconf_set()
1490 ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source); in rzg2l_pinctrl_pinconf_set()
1496 if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) { in rzg2l_pinctrl_pinconf_set()
1501 ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx, in rzg2l_pinctrl_pinconf_set()
1512 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val); in rzg2l_pinctrl_pinconf_set()
1513 pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua; in rzg2l_pinctrl_pinconf_set()
1596 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_request() local
1597 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_request()
1606 ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit); in rzg2l_gpio_request()
1614 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_request()
1617 reg8 = readb(pctrl->base + PMC(off)); in rzg2l_gpio_request()
1619 pctrl->data->pmc_writeb(pctrl, reg8, PMC(off)); in rzg2l_gpio_request()
1621 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_request()
1626 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, in rzg2l_gpio_set_direction() argument
1629 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_set_direction()
1636 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_set_direction()
1638 reg16 = readw(pctrl->base + PM(off)); in rzg2l_gpio_set_direction()
1642 writew(reg16, pctrl->base + PM(off)); in rzg2l_gpio_set_direction()
1644 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_set_direction()
1649 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_get_direction() local
1650 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_get_direction()
1655 if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) { in rzg2l_gpio_get_direction()
1658 reg16 = readw(pctrl->base + PM(off)); in rzg2l_gpio_get_direction()
1670 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_direction_input() local
1672 rzg2l_gpio_set_direction(pctrl, offset, false); in rzg2l_gpio_direction_input()
1680 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_set() local
1681 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_set()
1688 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_set()
1690 reg8 = readb(pctrl->base + P(off)); in rzg2l_gpio_set()
1693 writeb(reg8 | BIT(bit), pctrl->base + P(off)); in rzg2l_gpio_set()
1695 writeb(reg8 & ~BIT(bit), pctrl->base + P(off)); in rzg2l_gpio_set()
1697 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_set()
1703 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_direction_output() local
1706 rzg2l_gpio_set_direction(pctrl, offset, true); in rzg2l_gpio_direction_output()
1713 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_get() local
1714 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_get()
1720 reg16 = readw(pctrl->base + PM(off)); in rzg2l_gpio_get()
1724 return !!(readb(pctrl->base + PIN(off)) & BIT(bit)); in rzg2l_gpio_get()
1726 return !!(readb(pctrl->base + P(off)) & BIT(bit)); in rzg2l_gpio_get()
2211 static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) in rzg2l_gpio_get_gpioint() argument
2213 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; in rzg2l_gpio_get_gpioint()
2214 const struct rzg2l_pinctrl_data *data = pctrl->data; in rzg2l_gpio_get_gpioint()
2237 static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, in rzg2l_gpio_irq_endisable() argument
2240 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; in rzg2l_gpio_irq_endisable()
2247 addr = pctrl->base + ISEL(off); in rzg2l_gpio_irq_endisable()
2253 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_irq_endisable()
2258 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_irq_endisable()
2299 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); in rzg2l_gpio_irq_set_wake() local
2311 atomic_inc(&pctrl->wakeup_path); in rzg2l_gpio_irq_set_wake()
2313 atomic_dec(&pctrl->wakeup_path); in rzg2l_gpio_irq_set_wake()
2335 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_interrupt_input_mode() local
2336 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_interrupt_input_mode()
2343 reg8 = readb(pctrl->base + PMC(off)); in rzg2l_gpio_interrupt_input_mode()
2359 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); in rzg2l_gpio_child_to_parent_hwirq() local
2364 gpioint = rzg2l_gpio_get_gpioint(child, pctrl); in rzg2l_gpio_child_to_parent_hwirq()
2372 spin_lock_irqsave(&pctrl->bitmap_lock, flags); in rzg2l_gpio_child_to_parent_hwirq()
2373 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); in rzg2l_gpio_child_to_parent_hwirq()
2374 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); in rzg2l_gpio_child_to_parent_hwirq()
2380 rzg2l_gpio_irq_endisable(pctrl, child, true); in rzg2l_gpio_child_to_parent_hwirq()
2381 pctrl->hwirq[irq] = child; in rzg2l_gpio_child_to_parent_hwirq()
2409 static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) in rzg2l_gpio_irq_restore() argument
2411 struct irq_domain *domain = pctrl->gpio_chip.irq.domain; in rzg2l_gpio_irq_restore()
2419 if (!pctrl->hwirq[i]) in rzg2l_gpio_irq_restore()
2422 virq = irq_find_mapping(domain, pctrl->hwirq[i]); in rzg2l_gpio_irq_restore()
2424 dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n", in rzg2l_gpio_irq_restore()
2425 pctrl->hwirq[i]); in rzg2l_gpio_irq_restore()
2431 dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq); in rzg2l_gpio_irq_restore()
2439 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_irq_restore()
2443 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_irq_restore()
2446 dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq); in rzg2l_gpio_irq_restore()
2458 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); in rzg2l_gpio_irq_domain_free() local
2464 if (pctrl->hwirq[i] == hwirq) { in rzg2l_gpio_irq_domain_free()
2465 rzg2l_gpio_irq_endisable(pctrl, hwirq, false); in rzg2l_gpio_irq_domain_free()
2467 spin_lock_irqsave(&pctrl->bitmap_lock, flags); in rzg2l_gpio_irq_domain_free()
2468 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); in rzg2l_gpio_irq_domain_free()
2469 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); in rzg2l_gpio_irq_domain_free()
2470 pctrl->hwirq[i] = 0; in rzg2l_gpio_irq_domain_free()
2482 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); in rzg2l_init_irq_valid_mask() local
2483 struct gpio_chip *chip = &pctrl->gpio_chip; in rzg2l_init_irq_valid_mask()
2493 if (port >= pctrl->data->n_ports || in rzg2l_init_irq_valid_mask()
2495 pctrl->data->port_pin_configs[port]))) in rzg2l_init_irq_valid_mask()
2500 static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) in rzg2l_pinctrl_reg_cache_alloc() argument
2502 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; in rzg2l_pinctrl_reg_cache_alloc()
2505 cache = devm_kzalloc(pctrl->dev, sizeof(*cache), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2509 dedicated_cache = devm_kzalloc(pctrl->dev, sizeof(*dedicated_cache), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2513 cache->p = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->p), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2517 cache->pm = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pm), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2521 cache->pmc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pmc), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2525 cache->pfc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pfc), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2530 u32 n_dedicated_pins = pctrl->data->n_dedicated_pins; in rzg2l_pinctrl_reg_cache_alloc()
2532 cache->iolh[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->iolh[i]), in rzg2l_pinctrl_reg_cache_alloc()
2537 cache->ien[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->ien[i]), in rzg2l_pinctrl_reg_cache_alloc()
2543 dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, in rzg2l_pinctrl_reg_cache_alloc()
2549 dedicated_cache->ien[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, in rzg2l_pinctrl_reg_cache_alloc()
2556 pctrl->cache = cache; in rzg2l_pinctrl_reg_cache_alloc()
2557 pctrl->dedicated_cache = dedicated_cache; in rzg2l_pinctrl_reg_cache_alloc()
2562 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) in rzg2l_gpio_register() argument
2564 struct device_node *np = pctrl->dev->of_node; in rzg2l_gpio_register()
2565 struct gpio_chip *chip = &pctrl->gpio_chip; in rzg2l_gpio_register()
2566 const char *name = dev_name(pctrl->dev); in rzg2l_gpio_register()
2584 return dev_err_probe(pctrl->dev, ret, "Unable to parse gpio-ranges\n"); in rzg2l_gpio_register()
2587 of_args.args[2] != pctrl->data->n_port_pins) in rzg2l_gpio_register()
2588 return dev_err_probe(pctrl->dev, -EINVAL, in rzg2l_gpio_register()
2591 chip->names = pctrl->data->port_pins; in rzg2l_gpio_register()
2600 chip->parent = pctrl->dev; in rzg2l_gpio_register()
2607 girq->fwnode = dev_fwnode(pctrl->dev); in rzg2l_gpio_register()
2614 pctrl->gpio_range.id = 0; in rzg2l_gpio_register()
2615 pctrl->gpio_range.pin_base = 0; in rzg2l_gpio_register()
2616 pctrl->gpio_range.base = 0; in rzg2l_gpio_register()
2617 pctrl->gpio_range.npins = chip->ngpio; in rzg2l_gpio_register()
2618 pctrl->gpio_range.name = chip->label; in rzg2l_gpio_register()
2619 pctrl->gpio_range.gc = chip; in rzg2l_gpio_register()
2620 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); in rzg2l_gpio_register()
2622 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO controller\n"); in rzg2l_gpio_register()
2624 dev_dbg(pctrl->dev, "Registered gpio controller\n"); in rzg2l_gpio_register()
2629 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) in rzg2l_pinctrl_register() argument
2631 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_register()
2637 pctrl->desc.name = DRV_NAME; in rzg2l_pinctrl_register()
2638 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; in rzg2l_pinctrl_register()
2639 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; in rzg2l_pinctrl_register()
2640 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; in rzg2l_pinctrl_register()
2641 pctrl->desc.confops = &rzg2l_pinctrl_confops; in rzg2l_pinctrl_register()
2642 pctrl->desc.owner = THIS_MODULE; in rzg2l_pinctrl_register()
2643 if (pctrl->data->num_custom_params) { in rzg2l_pinctrl_register()
2644 pctrl->desc.num_custom_params = pctrl->data->num_custom_params; in rzg2l_pinctrl_register()
2645 pctrl->desc.custom_params = pctrl->data->custom_params; in rzg2l_pinctrl_register()
2647 pctrl->desc.custom_conf_items = pctrl->data->custom_conf_items; in rzg2l_pinctrl_register()
2651 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); in rzg2l_pinctrl_register()
2655 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, in rzg2l_pinctrl_register()
2660 pctrl->pins = pins; in rzg2l_pinctrl_register()
2661 pctrl->desc.pins = pins; in rzg2l_pinctrl_register()
2663 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { in rzg2l_pinctrl_register()
2665 pins[i].name = pctrl->data->port_pins[i]; in rzg2l_pinctrl_register()
2668 pin_data[i] = pctrl->data->port_pin_configs[j]; in rzg2l_pinctrl_register()
2670 pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl, in rzg2l_pinctrl_register()
2677 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { in rzg2l_pinctrl_register()
2678 unsigned int index = pctrl->data->n_port_pins + i; in rzg2l_pinctrl_register()
2681 pins[index].name = pctrl->data->dedicated_pins[i].name; in rzg2l_pinctrl_register()
2682 pin_data[index] = pctrl->data->dedicated_pins[i].config; in rzg2l_pinctrl_register()
2686 pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings), in rzg2l_pinctrl_register()
2688 if (!pctrl->settings) in rzg2l_pinctrl_register()
2691 for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) { in rzg2l_pinctrl_register()
2693 pctrl->settings[i].power_source = 3300; in rzg2l_pinctrl_register()
2695 ret = rzg2l_get_power_source(pctrl, i, pin_data[i]); in rzg2l_pinctrl_register()
2698 pctrl->settings[i].power_source = ret; in rzg2l_pinctrl_register()
2702 ret = rzg2l_pinctrl_reg_cache_alloc(pctrl); in rzg2l_pinctrl_register()
2706 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, in rzg2l_pinctrl_register()
2707 &pctrl->pctl); in rzg2l_pinctrl_register()
2709 return dev_err_probe(pctrl->dev, ret, "pinctrl registration failed\n"); in rzg2l_pinctrl_register()
2711 ret = pinctrl_enable(pctrl->pctl); in rzg2l_pinctrl_register()
2713 dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n"); in rzg2l_pinctrl_register()
2715 ret = rzg2l_gpio_register(pctrl); in rzg2l_pinctrl_register()
2717 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO chip\n"); in rzg2l_pinctrl_register()
2724 struct rzg2l_pinctrl *pctrl; in rzg2l_pinctrl_probe() local
2739 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in rzg2l_pinctrl_probe()
2740 if (!pctrl) in rzg2l_pinctrl_probe()
2743 pctrl->dev = &pdev->dev; in rzg2l_pinctrl_probe()
2745 pctrl->data = of_device_get_match_data(&pdev->dev); in rzg2l_pinctrl_probe()
2746 if (!pctrl->data) in rzg2l_pinctrl_probe()
2749 pctrl->base = devm_platform_ioremap_resource(pdev, 0); in rzg2l_pinctrl_probe()
2750 if (IS_ERR(pctrl->base)) in rzg2l_pinctrl_probe()
2751 return PTR_ERR(pctrl->base); in rzg2l_pinctrl_probe()
2753 pctrl->clk = devm_clk_get_enabled(pctrl->dev, NULL); in rzg2l_pinctrl_probe()
2754 if (IS_ERR(pctrl->clk)) { in rzg2l_pinctrl_probe()
2755 return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->clk), in rzg2l_pinctrl_probe()
2759 spin_lock_init(&pctrl->lock); in rzg2l_pinctrl_probe()
2760 spin_lock_init(&pctrl->bitmap_lock); in rzg2l_pinctrl_probe()
2761 mutex_init(&pctrl->mutex); in rzg2l_pinctrl_probe()
2762 atomic_set(&pctrl->wakeup_path, 0); in rzg2l_pinctrl_probe()
2764 platform_set_drvdata(pdev, pctrl); in rzg2l_pinctrl_probe()
2766 ret = rzg2l_pinctrl_register(pctrl); in rzg2l_pinctrl_probe()
2770 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); in rzg2l_pinctrl_probe()
2774 static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspend) in rzg2l_pinctrl_pm_setup_regs() argument
2776 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; in rzg2l_pinctrl_pm_setup_regs()
2777 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_pm_setup_regs()
2785 cfg = pctrl->data->port_pin_configs[port]; in rzg2l_pinctrl_pm_setup_regs()
2794 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); in rzg2l_pinctrl_pm_setup_regs()
2800 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]); in rzg2l_pinctrl_pm_setup_regs()
2802 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), in rzg2l_pinctrl_pm_setup_regs()
2805 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4, in rzg2l_pinctrl_pm_setup_regs()
2810 RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]); in rzg2l_pinctrl_pm_setup_regs()
2811 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]); in rzg2l_pinctrl_pm_setup_regs()
2814 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), in rzg2l_pinctrl_pm_setup_regs()
2817 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4, in rzg2l_pinctrl_pm_setup_regs()
2824 static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend) in rzg2l_pinctrl_pm_setup_dedicated_regs() argument
2826 struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache; in rzg2l_pinctrl_pm_setup_dedicated_regs()
2831 * Make sure entries in pctrl->data->n_dedicated_pins[] having the same in rzg2l_pinctrl_pm_setup_dedicated_regs()
2834 for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { in rzg2l_pinctrl_pm_setup_dedicated_regs()
2840 cfg = pctrl->data->dedicated_pins[i].config; in rzg2l_pinctrl_pm_setup_dedicated_regs()
2842 if (i + 1 < pctrl->data->n_dedicated_pins) { in rzg2l_pinctrl_pm_setup_dedicated_regs()
2843 next_cfg = pctrl->data->dedicated_pins[i + 1].config; in rzg2l_pinctrl_pm_setup_dedicated_regs()
2859 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), in rzg2l_pinctrl_pm_setup_dedicated_regs()
2863 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), in rzg2l_pinctrl_pm_setup_dedicated_regs()
2870 pctrl->base + IOLH(off) + 4, in rzg2l_pinctrl_pm_setup_dedicated_regs()
2875 pctrl->base + IEN(off) + 4, in rzg2l_pinctrl_pm_setup_dedicated_regs()
2883 static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) in rzg2l_pinctrl_pm_setup_pfc() argument
2885 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; in rzg2l_pinctrl_pm_setup_pfc()
2888 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_pm_setup_pfc()
2889 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); in rzg2l_pinctrl_pm_setup_pfc()
2900 cfg = pctrl->data->port_pin_configs[port]; in rzg2l_pinctrl_pm_setup_pfc()
2905 pm = readw(pctrl->base + PM(off)); in rzg2l_pinctrl_pm_setup_pfc()
2907 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_pm_setup_pfc()
2915 writew(pm, pctrl->base + PM(off)); in rzg2l_pinctrl_pm_setup_pfc()
2919 writeb(pmc, pctrl->base + PMC(off)); in rzg2l_pinctrl_pm_setup_pfc()
2924 writel(pfc, pctrl->base + PFC(off)); in rzg2l_pinctrl_pm_setup_pfc()
2928 writeb(pmc, pctrl->base + PMC(off)); in rzg2l_pinctrl_pm_setup_pfc()
2932 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); in rzg2l_pinctrl_pm_setup_pfc()
2933 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_pm_setup_pfc()
2938 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); in rzg2l_pinctrl_suspend_noirq() local
2939 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_suspend_noirq()
2941 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_suspend_noirq()
2943 rzg2l_pinctrl_pm_setup_regs(pctrl, true); in rzg2l_pinctrl_suspend_noirq()
2944 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true); in rzg2l_pinctrl_suspend_noirq()
2948 cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); in rzg2l_pinctrl_suspend_noirq()
2950 cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); in rzg2l_pinctrl_suspend_noirq()
2953 cache->qspi = readb(pctrl->base + QSPI); in rzg2l_pinctrl_suspend_noirq()
2954 cache->eth_mode = readb(pctrl->base + ETH_MODE); in rzg2l_pinctrl_suspend_noirq()
2956 if (!atomic_read(&pctrl->wakeup_path)) in rzg2l_pinctrl_suspend_noirq()
2957 clk_disable_unprepare(pctrl->clk); in rzg2l_pinctrl_suspend_noirq()
2966 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); in rzg2l_pinctrl_resume_noirq() local
2967 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_resume_noirq()
2969 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_resume_noirq()
2972 if (!atomic_read(&pctrl->wakeup_path)) { in rzg2l_pinctrl_resume_noirq()
2973 ret = clk_prepare_enable(pctrl->clk); in rzg2l_pinctrl_resume_noirq()
2978 writeb(cache->qspi, pctrl->base + QSPI); in rzg2l_pinctrl_resume_noirq()
2979 writeb(cache->eth_mode, pctrl->base + ETH_MODE); in rzg2l_pinctrl_resume_noirq()
2982 writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); in rzg2l_pinctrl_resume_noirq()
2984 writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); in rzg2l_pinctrl_resume_noirq()
2987 rzg2l_pinctrl_pm_setup_pfc(pctrl); in rzg2l_pinctrl_resume_noirq()
2988 rzg2l_pinctrl_pm_setup_regs(pctrl, false); in rzg2l_pinctrl_resume_noirq()
2989 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, false); in rzg2l_pinctrl_resume_noirq()
2990 rzg2l_gpio_irq_restore(pctrl); in rzg2l_pinctrl_resume_noirq()
2995 static void rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock) in rzg2l_pwpr_pfc_lock_unlock() argument
2997 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; in rzg2l_pwpr_pfc_lock_unlock()
3001 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ in rzg2l_pwpr_pfc_lock_unlock()
3002 writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ in rzg2l_pwpr_pfc_lock_unlock()
3005 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ in rzg2l_pwpr_pfc_lock_unlock()
3006 writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ in rzg2l_pwpr_pfc_lock_unlock()
3010 static void rzv2h_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock) in rzv2h_pwpr_pfc_lock_unlock() argument
3012 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; in rzv2h_pwpr_pfc_lock_unlock()
3017 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3018 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3021 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3022 writeb(PWPR_REGWE_A | pwpr, pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()