Lines Matching +full:single +full:- +full:chip
1 // SPDX-License-Identifier: GPL-2.0
25 #define DRIVER_NAME "pinctrl-rza2"
54 #define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */
55 #define RZA2_PODR(port) (0x0040 + (port)) /* Output Data 8-bit */
56 #define RZA2_PIDR(port) (0x0060 + (port)) /* Input Data 8-bit */
57 #define RZA2_PMR(port) (0x0080 + (port)) /* Mode 8-bit */
58 #define RZA2_DSCR(port) (0x0140 + (port) * 2) /* Drive 16-bit */
59 #define RZA2_PFS(port, pin) (0x0200 + ((port) * 8) + (pin)) /* Fnct 8-bit */
61 #define RZA2_PWPR 0x02ff /* Write Protect 8-bit */
62 #define RZA2_PFENET 0x0820 /* Ethernet Pins 8-bit */
63 #define RZA2_PPOC 0x0900 /* Dedicated Pins 32-bit */
64 #define RZA2_PHMOMO 0x0980 /* Peripheral Pins 32-bit */
65 #define RZA2_PCKIO 0x09d0 /* CKIO Drive 8-bit */
82 /* Set pin to 'Non-use (Hi-z input protection)' */ in rza2_set_pin_function()
130 static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset) in rza2_chip_get_direction() argument
132 struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip); in rza2_chip_get_direction()
137 reg16 = readw(priv->base + RZA2_PDR(port)); in rza2_chip_get_direction()
147 * This GPIO controller has a default Hi-Z state that is not input or in rza2_chip_get_direction()
150 rza2_pin_to_gpio(priv->base, offset, 1); in rza2_chip_get_direction()
155 static int rza2_chip_direction_input(struct gpio_chip *chip, in rza2_chip_direction_input() argument
158 struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip); in rza2_chip_direction_input()
160 rza2_pin_to_gpio(priv->base, offset, 1); in rza2_chip_direction_input()
165 static int rza2_chip_get(struct gpio_chip *chip, unsigned int offset) in rza2_chip_get() argument
167 struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip); in rza2_chip_get()
171 return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin)); in rza2_chip_get()
174 static void rza2_chip_set(struct gpio_chip *chip, unsigned int offset, in rza2_chip_set() argument
177 struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip); in rza2_chip_set()
182 new_value = readb(priv->base + RZA2_PODR(port)); in rza2_chip_set()
189 writeb(new_value, priv->base + RZA2_PODR(port)); in rza2_chip_set()
192 static int rza2_chip_direction_output(struct gpio_chip *chip, in rza2_chip_direction_output() argument
195 struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip); in rza2_chip_direction_output()
197 rza2_chip_set(chip, offset, val); in rza2_chip_direction_output()
198 rza2_pin_to_gpio(priv->base, offset, 0); in rza2_chip_direction_output()
229 static struct gpio_chip chip = { variable
231 .base = -1,
241 struct device_node *np = priv->dev->of_node; in rza2_gpio_register()
245 chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np); in rza2_gpio_register()
246 chip.parent = priv->dev; in rza2_gpio_register()
247 chip.ngpio = priv->npins; in rza2_gpio_register()
249 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, in rza2_gpio_register()
252 dev_err(priv->dev, "Unable to parse gpio-ranges\n"); in rza2_gpio_register()
258 (of_args.args[2] != priv->npins)) { in rza2_gpio_register()
259 dev_err(priv->dev, "gpio-ranges does not match selected SOC\n"); in rza2_gpio_register()
260 return -EINVAL; in rza2_gpio_register()
262 priv->gpio_range.id = 0; in rza2_gpio_register()
263 priv->gpio_range.pin_base = priv->gpio_range.base = 0; in rza2_gpio_register()
264 priv->gpio_range.npins = priv->npins; in rza2_gpio_register()
265 priv->gpio_range.name = chip.label; in rza2_gpio_register()
266 priv->gpio_range.gc = &chip; in rza2_gpio_register()
268 /* Register our gpio chip with gpiolib */ in rza2_gpio_register()
269 ret = devm_gpiochip_add_data(priv->dev, &chip, priv); in rza2_gpio_register()
274 pinctrl_add_gpio_range(priv->pctl, &priv->gpio_range); in rza2_gpio_register()
276 dev_dbg(priv->dev, "Registered gpio controller\n"); in rza2_gpio_register()
287 pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL); in rza2_pinctrl_register()
289 return -ENOMEM; in rza2_pinctrl_register()
291 priv->pins = pins; in rza2_pinctrl_register()
292 priv->desc.pins = pins; in rza2_pinctrl_register()
293 priv->desc.npins = priv->npins; in rza2_pinctrl_register()
295 for (i = 0; i < priv->npins; i++) { in rza2_pinctrl_register()
300 ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv, in rza2_pinctrl_register()
301 &priv->pctl); in rza2_pinctrl_register()
303 dev_err(priv->dev, "pinctrl registration failed\n"); in rza2_pinctrl_register()
307 ret = pinctrl_enable(priv->pctl); in rza2_pinctrl_register()
309 dev_err(priv->dev, "pinctrl enable failed\n"); in rza2_pinctrl_register()
315 dev_err(priv->dev, "GPIO registration failed\n"); in rza2_pinctrl_register()
323 * For each DT node, create a single pin mapping. That pin mapping will only
324 * contain a single group of pins, and that group of pins will only have a
325 * single function that can be selected.
341 dev_info(priv->dev, "Missing pinmux property\n"); in rza2_dt_node_to_map()
342 return -ENOENT; in rza2_dt_node_to_map()
344 npins = of_pins->length / sizeof(u32); in rza2_dt_node_to_map()
346 pins = devm_kcalloc(priv->dev, npins, sizeof(*pins), GFP_KERNEL); in rza2_dt_node_to_map()
347 psel_val = devm_kcalloc(priv->dev, npins, sizeof(*psel_val), in rza2_dt_node_to_map()
349 pin_fn = devm_kzalloc(priv->dev, sizeof(*pin_fn), GFP_KERNEL); in rza2_dt_node_to_map()
351 return -ENOMEM; in rza2_dt_node_to_map()
364 mutex_lock(&priv->mutex); in rza2_dt_node_to_map()
366 /* Register a single pin group listing all the pins we read from DT */ in rza2_dt_node_to_map()
367 gsel = pinctrl_generic_add_group(pctldev, np->name, pins, npins, NULL); in rza2_dt_node_to_map()
374 * Register a single group function where the 'data' is an array PSEL in rza2_dt_node_to_map()
377 pin_fn[0] = np->name; in rza2_dt_node_to_map()
378 fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1, in rza2_dt_node_to_map()
385 dev_dbg(priv->dev, "Parsed %pOF with %d pins\n", np, npins); in rza2_dt_node_to_map()
391 ret = -ENOMEM; in rza2_dt_node_to_map()
395 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; in rza2_dt_node_to_map()
396 (*map)->data.mux.group = np->name; in rza2_dt_node_to_map()
397 (*map)->data.mux.function = np->name; in rza2_dt_node_to_map()
400 mutex_unlock(&priv->mutex); in rza2_dt_node_to_map()
411 mutex_unlock(&priv->mutex); in rza2_dt_node_to_map()
413 dev_err(priv->dev, "Unable to parse DT node %s\n", np->name); in rza2_dt_node_to_map()
442 return -EINVAL; in rza2_set_mux()
446 return -EINVAL; in rza2_set_mux()
448 psel_val = func->data; in rza2_set_mux()
450 for (i = 0; i < grp->grp.npins; ++i) { in rza2_set_mux()
451 dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n", in rza2_set_mux()
452 port_names[RZA2_PIN_ID_TO_PORT(grp->grp.pins[i])], in rza2_set_mux()
453 RZA2_PIN_ID_TO_PIN(grp->grp.pins[i]), in rza2_set_mux()
456 priv->base, in rza2_set_mux()
457 RZA2_PIN_ID_TO_PORT(grp->grp.pins[i]), in rza2_set_mux()
458 RZA2_PIN_ID_TO_PIN(grp->grp.pins[i]), in rza2_set_mux()
478 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in rza2_pinctrl_probe()
480 return -ENOMEM; in rza2_pinctrl_probe()
482 priv->dev = &pdev->dev; in rza2_pinctrl_probe()
484 priv->base = devm_platform_ioremap_resource(pdev, 0); in rza2_pinctrl_probe()
485 if (IS_ERR(priv->base)) in rza2_pinctrl_probe()
486 return PTR_ERR(priv->base); in rza2_pinctrl_probe()
488 mutex_init(&priv->mutex); in rza2_pinctrl_probe()
492 priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) * in rza2_pinctrl_probe()
495 priv->desc.name = DRIVER_NAME; in rza2_pinctrl_probe()
496 priv->desc.pctlops = &rza2_pinctrl_ops; in rza2_pinctrl_probe()
497 priv->desc.pmxops = &rza2_pinmux_ops; in rza2_pinctrl_probe()
498 priv->desc.owner = THIS_MODULE; in rza2_pinctrl_probe()
504 dev_info(&pdev->dev, "Registered ports P0 - P%c\n", in rza2_pinctrl_probe()
505 port_names[priv->desc.npins / RZA2_PINS_PER_PORT - 1]); in rza2_pinctrl_probe()
511 { .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, },