pinctrl/qcom/pinctrl-sm6115.c

42 		.ctl_reg = 0x1000 * id,		\
43 		.io_reg = 0x4 + 0x1000 * id,		\
44 		.intr_cfg_reg = 0x8 + 0x1000 * id,	\
45 		.intr_status_reg = 0xc + 0x1000 * id,	\
46 		.intr_target_reg = 0x8 + 0x1000 * id,	\
49 		.pull_bit = 0,			\
52 		.in_bit = 0,			\
54 		.intr_enable_bit = 0,		\
55 		.intr_status_bit = 0,		\
70 		.io_reg = 0,				\
71 		.intr_cfg_reg = 0,			\
72 		.intr_status_reg = 0,			\
73 		.intr_target_reg = 0,			\
96 		.io_reg = offset + 0x4,			\
97 		.intr_cfg_reg = 0,			\
98 		.intr_status_reg = 0,			\
99 		.intr_target_reg = 0,			\
103 		.drv_bit = 0,				\
106 		.out_bit = 0,				\
116 	PINCTRL_PIN(0, "GPIO_0"),
241 DECLARE_MSM_GPIO_PINS(0);
747 	[0] = PINGROUP(0, WEST, qup0, m_voc, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _),
860 	[113] = UFS_RESET(ufs_reset, 0x78000),
861 	[114] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x75000, 15, 0),
862 	[115] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x75000, 13, 6),
863 	[116] = SDC_QDSD_PINGROUP(sdc1_cmd, WEST, 0x75000, 11, 3),
864 	[117] = SDC_QDSD_PINGROUP(sdc1_data, WEST, 0x75000, 9, 0),
865 	[118] = SDC_QDSD_PINGROUP(sdc2_clk, SOUTH, 0x73000, 14, 6),
866 	[119] = SDC_QDSD_PINGROUP(sdc2_cmd, SOUTH, 0x73000, 11, 3),
867 	[120] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x73000, 9, 0),
871 	{ 0, 84 }, { 3, 75 }, { 4, 16 }, { 6, 59 }, { 8, 63 }, { 11, 17 }, { 13, 18 },