Lines Matching +full:wakeup +full:- +full:gpios

1 /* SPDX-License-Identifier: GPL-2.0-only */
38  * struct msm_pingroup - Qualcomm pingroup definition
62  *			  wakeup events.
63  * @intr_wakeup_enable_bit: Offset in @intr_target_reg to enable wakeup events for the GPIO.
118  * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins
119  * @gpio:          The GPIOs that are wakeup capable
120  * @wakeirq:       The interrupt at the always-on interrupt controller
128  * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
135  * @ngpio:	    The number of pingroups the driver should expose as GPIOs.
137  * @wakeirq_map:    The map of wakeup capable GPIOs and the pin at PDC/MPM
139  * @wakeirq_dual_edge_errata: If true then GPIOs using the wakeirq_map need
143  * @egpio_func: If non-zero then this SoC supports eGPIO. Even though in
144  *              hardware this is a mux 1-level above the TLMM, we'll treat