Lines Matching full:pctrl
43 * @pctrl: pinctrl handle.
63 struct pinctrl_dev *pctrl; member
86 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
89 return readl(pctrl->regs[g->tile] + g->name##_reg); \
91 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
94 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
103 static void msm_ack_intr_status(struct msm_pinctrl *pctrl, in MSM_ACCESSOR()
108 msm_writel_intr_status(val, pctrl, g); in MSM_ACCESSOR()
113 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_groups_count() local
115 return pctrl->soc->ngroups; in msm_get_groups_count()
121 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_group_name() local
123 return pctrl->soc->groups[group].grp.name; in msm_get_group_name()
131 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_group_pins() local
133 *pins = pctrl->soc->groups[group].grp.pins; in msm_get_group_pins()
134 *num_pins = pctrl->soc->groups[group].grp.npins; in msm_get_group_pins()
148 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_request() local
149 struct gpio_chip *chip = &pctrl->chip; in msm_pinmux_request()
156 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_functions_count() local
158 return pctrl->soc->nfunctions; in msm_get_functions_count()
164 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_function_name() local
166 return pctrl->soc->functions[function].name; in msm_get_function_name()
174 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_function_groups() local
176 *groups = pctrl->soc->functions[function].groups; in msm_get_function_groups()
177 *num_groups = pctrl->soc->functions[function].ngroups; in msm_get_function_groups()
185 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_set_mux() local
186 struct gpio_chip *gc = &pctrl->chip; in msm_pinmux_set_mux()
189 unsigned int gpio_func = pctrl->soc->gpio_func; in msm_pinmux_set_mux()
190 unsigned int egpio_func = pctrl->soc->egpio_func; in msm_pinmux_set_mux()
196 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
218 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux)) in msm_pinmux_set_mux()
221 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_pinmux_set_mux()
223 val = msm_readl_ctl(pctrl, g); in msm_pinmux_set_mux()
232 !test_and_set_bit(group, pctrl->ever_gpio)) { in msm_pinmux_set_mux()
233 u32 io_val = msm_readl_io(pctrl, g); in msm_pinmux_set_mux()
237 msm_writel_io(io_val | BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
240 msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
255 msm_writel_ctl(val, pctrl, g); in msm_pinmux_set_mux()
257 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_pinmux_set_mux()
260 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) { in msm_pinmux_set_mux()
265 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_pinmux_set_mux()
268 msm_ack_intr_status(pctrl, g); in msm_pinmux_set_mux()
280 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_request_gpio() local
281 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio()
287 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset); in msm_pinmux_request_gpio()
299 static int msm_config_reg(struct msm_pinctrl *pctrl, in msm_config_reg() argument
353 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_config_group_get() local
362 if (!gpiochip_line_is_valid(&pctrl->chip, group)) in msm_config_group_get()
365 g = &pctrl->soc->groups[group]; in msm_config_group_get()
367 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_get()
371 val = msm_readl_ctl(pctrl, g); in msm_config_group_get()
387 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
395 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
418 val = msm_readl_io(pctrl, g); in msm_config_group_get()
440 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_config_group_set() local
450 g = &pctrl->soc->groups[group]; in msm_config_group_set()
456 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_set()
469 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
475 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
494 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
495 val = msm_readl_io(pctrl, g); in msm_config_group_set()
500 msm_writel_io(val, pctrl, g); in msm_config_group_set()
501 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
538 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", in msm_config_group_set()
545 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); in msm_config_group_set()
549 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
550 val = msm_readl_ctl(pctrl, g); in msm_config_group_set()
553 msm_writel_ctl(val, pctrl, g); in msm_config_group_set()
554 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
569 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_direction_input() local
573 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
575 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_input()
577 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_input()
579 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_input()
581 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_input()
589 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_direction_output() local
593 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
595 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_output()
597 val = msm_readl_io(pctrl, g); in msm_gpio_direction_output()
602 msm_writel_io(val, pctrl, g); in msm_gpio_direction_output()
604 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_output()
606 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_output()
608 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_output()
615 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_get_direction() local
619 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
621 val = msm_readl_ctl(pctrl, g); in msm_gpio_get_direction()
630 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_get() local
633 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
635 val = msm_readl_io(pctrl, g); in msm_gpio_get()
642 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_set() local
646 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
648 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_set()
650 val = msm_readl_io(pctrl, g); in msm_gpio_set()
655 msm_writel_io(val, pctrl, g); in msm_gpio_set()
657 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_set()
669 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_dbg_show_one() local
694 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
695 ctl_reg = msm_readl_ctl(pctrl, g); in msm_gpio_dbg_show_one()
696 io_reg = msm_readl_io(pctrl, g); in msm_gpio_dbg_show_one()
703 if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present)) in msm_gpio_dbg_show_one()
719 if (pctrl->soc->pull_no_keeper) in msm_gpio_dbg_show_one()
743 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_init_valid_mask() local
746 const int *reserved = pctrl->soc->reserved_gpios; in msm_gpio_init_valid_mask()
753 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); in msm_gpio_init_valid_mask()
763 len = ret = device_property_count_u16(pctrl->dev, "gpios"); in msm_gpio_init_valid_mask()
774 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); in msm_gpio_init_valid_mask()
776 dev_err(pctrl->dev, "could not read list of GPIOs\n"); in msm_gpio_init_valid_mask()
820 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, in msm_gpio_update_dual_edge_pos() argument
829 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
831 pol = msm_readl_intr_cfg(pctrl, g); in msm_gpio_update_dual_edge_pos()
833 msm_writel_intr_cfg(pol, pctrl, g); in msm_gpio_update_dual_edge_pos()
835 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
836 intstat = msm_readl_intr_status(pctrl, g); in msm_gpio_update_dual_edge_pos()
840 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", in msm_gpio_update_dual_edge_pos()
847 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_mask() local
855 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_mask()
858 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
860 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_mask()
862 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_mask()
887 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_mask()
889 clear_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_mask()
891 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_mask()
897 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_unmask() local
905 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_unmask()
908 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
910 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_unmask()
912 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_unmask()
915 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_unmask()
917 set_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_unmask()
919 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_unmask()
925 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_enable() local
932 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_enable()
939 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_disable() local
944 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_disable()
962 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_update_dual_edge_parent() local
963 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_update_dual_edge_parent()
969 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
982 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
993 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n"); in msm_gpio_update_dual_edge_parent()
999 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_ack() local
1003 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_ack()
1004 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
1009 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
1011 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_ack()
1013 msm_ack_intr_status(pctrl, g); in msm_gpio_irq_ack()
1015 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
1016 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_ack()
1018 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_ack()
1033 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_needs_dual_edge_parent_workaround() local
1036 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data && in msm_gpio_needs_dual_edge_parent_workaround()
1037 test_bit(d->hwirq, pctrl->skip_wake_irqs); in msm_gpio_needs_dual_edge_parent_workaround()
1043 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_type() local
1051 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1060 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_set_type()
1061 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1066 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
1068 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1074 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1076 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1085 if (pctrl->intr_target_use_scm) { in msm_gpio_irq_set_type()
1086 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; in msm_gpio_irq_set_type()
1095 dev_err(pctrl->dev, in msm_gpio_irq_set_type()
1099 val = msm_readl_intr_target(pctrl, g); in msm_gpio_irq_set_type()
1102 msm_writel_intr_target(val, pctrl, g); in msm_gpio_irq_set_type()
1110 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_set_type()
1159 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_set_type()
1167 msm_ack_intr_status(pctrl, g); in msm_gpio_irq_set_type()
1169 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_set_type()
1170 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_set_type()
1172 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1185 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_wake() local
1193 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_wake()
1196 return irq_set_irq_wake(pctrl->irq, on); in msm_gpio_irq_set_wake()
1202 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_reqres() local
1203 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_reqres()
1210 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); in msm_gpio_irq_reqres()
1238 if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { in msm_gpio_irq_reqres()
1241 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_reqres()
1243 intr_cfg = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_reqres()
1246 msm_writel_intr_cfg(intr_cfg, pctrl, g); in msm_gpio_irq_reqres()
1249 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_reqres()
1261 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_relres() local
1262 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_relres()
1266 if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { in msm_gpio_irq_relres()
1269 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_relres()
1271 intr_cfg = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_relres()
1274 msm_writel_intr_cfg(intr_cfg, pctrl, g); in msm_gpio_irq_relres()
1277 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_relres()
1288 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_affinity() local
1290 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_affinity()
1299 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_vcpu_affinity() local
1301 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_vcpu_affinity()
1311 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_handler() local
1323 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { in msm_gpio_irq_handler()
1324 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
1325 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_handler()
1345 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_wakeirq() local
1352 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_wakeirq()
1353 map = &pctrl->soc->wakeirq_map[i]; in msm_gpio_wakeirq()
1363 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) in msm_gpio_needs_valid_mask() argument
1365 if (pctrl->soc->reserved_gpios) in msm_gpio_needs_valid_mask()
1368 return device_property_count_u16(pctrl->dev, "gpios") > 0; in msm_gpio_needs_valid_mask()
1391 static int msm_gpio_init(struct msm_pinctrl *pctrl) in msm_gpio_init() argument
1396 unsigned gpio, ngpio = pctrl->soc->ngpios; in msm_gpio_init()
1403 chip = &pctrl->chip; in msm_gpio_init()
1406 chip->label = dev_name(pctrl->dev); in msm_gpio_init()
1407 chip->parent = pctrl->dev; in msm_gpio_init()
1409 if (msm_gpio_needs_valid_mask(pctrl)) in msm_gpio_init()
1412 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); in msm_gpio_init()
1425 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_init()
1426 gpio = pctrl->soc->wakeirq_map[i].gpio; in msm_gpio_init()
1427 set_bit(gpio, pctrl->skip_wake_irqs); in msm_gpio_init()
1434 girq->fwnode = dev_fwnode(pctrl->dev); in msm_gpio_init()
1436 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), in msm_gpio_init()
1442 girq->parents[0] = pctrl->irq; in msm_gpio_init()
1444 ret = gpiochip_add_data(&pctrl->chip, pctrl); in msm_gpio_init()
1446 dev_err(pctrl->dev, "Failed register gpiochip\n"); in msm_gpio_init()
1460 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { in msm_gpio_init()
1461 ret = gpiochip_add_pin_range(&pctrl->chip, in msm_gpio_init()
1462 dev_name(pctrl->dev), 0, 0, chip->ngpio); in msm_gpio_init()
1464 dev_err(pctrl->dev, "Failed to add pin range\n"); in msm_gpio_init()
1465 gpiochip_remove(&pctrl->chip); in msm_gpio_init()
1476 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); in msm_ps_hold_restart() local
1478 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); in msm_ps_hold_restart()
1490 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) in msm_pinctrl_setup_pm_reset() argument
1493 const struct pinfunction *func = pctrl->soc->functions; in msm_pinctrl_setup_pm_reset()
1495 for (i = 0; i < pctrl->soc->nfunctions; i++) in msm_pinctrl_setup_pm_reset()
1497 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; in msm_pinctrl_setup_pm_reset()
1498 pctrl->restart_nb.priority = 128; in msm_pinctrl_setup_pm_reset()
1499 if (register_restart_handler(&pctrl->restart_nb)) in msm_pinctrl_setup_pm_reset()
1500 dev_err(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1502 poweroff_pctrl = pctrl; in msm_pinctrl_setup_pm_reset()
1510 struct msm_pinctrl *pctrl = dev_get_drvdata(dev); in msm_pinctrl_suspend() local
1512 return pinctrl_force_sleep(pctrl->pctrl); in msm_pinctrl_suspend()
1517 struct msm_pinctrl *pctrl = dev_get_drvdata(dev); in msm_pinctrl_resume() local
1519 return pinctrl_force_default(pctrl->pctrl); in msm_pinctrl_resume()
1530 struct msm_pinctrl *pctrl; in msm_pinctrl_probe() local
1535 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in msm_pinctrl_probe()
1536 if (!pctrl) in msm_pinctrl_probe()
1539 pctrl->dev = &pdev->dev; in msm_pinctrl_probe()
1540 pctrl->soc = soc_data; in msm_pinctrl_probe()
1541 pctrl->chip = msm_gpio_template; in msm_pinctrl_probe()
1542 pctrl->intr_target_use_scm = of_device_is_compatible( in msm_pinctrl_probe()
1543 pctrl->dev->of_node, in msm_pinctrl_probe()
1546 raw_spin_lock_init(&pctrl->lock); in msm_pinctrl_probe()
1552 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1553 if (IS_ERR(pctrl->regs[i])) in msm_pinctrl_probe()
1554 return PTR_ERR(pctrl->regs[i]); in msm_pinctrl_probe()
1557 pctrl->regs[0] = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in msm_pinctrl_probe()
1558 if (IS_ERR(pctrl->regs[0])) in msm_pinctrl_probe()
1559 return PTR_ERR(pctrl->regs[0]); in msm_pinctrl_probe()
1561 pctrl->phys_base[0] = res->start; in msm_pinctrl_probe()
1564 msm_pinctrl_setup_pm_reset(pctrl); in msm_pinctrl_probe()
1566 pctrl->irq = platform_get_irq(pdev, 0); in msm_pinctrl_probe()
1567 if (pctrl->irq < 0) in msm_pinctrl_probe()
1568 return pctrl->irq; in msm_pinctrl_probe()
1570 pctrl->desc.owner = THIS_MODULE; in msm_pinctrl_probe()
1571 pctrl->desc.pctlops = &msm_pinctrl_ops; in msm_pinctrl_probe()
1572 pctrl->desc.pmxops = &msm_pinmux_ops; in msm_pinctrl_probe()
1573 pctrl->desc.confops = &msm_pinconf_ops; in msm_pinctrl_probe()
1574 pctrl->desc.name = dev_name(&pdev->dev); in msm_pinctrl_probe()
1575 pctrl->desc.pins = pctrl->soc->pins; in msm_pinctrl_probe()
1576 pctrl->desc.npins = pctrl->soc->npins; in msm_pinctrl_probe()
1578 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in msm_pinctrl_probe()
1579 if (IS_ERR(pctrl->pctrl)) { in msm_pinctrl_probe()
1581 return PTR_ERR(pctrl->pctrl); in msm_pinctrl_probe()
1584 ret = msm_gpio_init(pctrl); in msm_pinctrl_probe()
1588 platform_set_drvdata(pdev, pctrl); in msm_pinctrl_probe()
1598 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); in msm_pinctrl_remove() local
1600 gpiochip_remove(&pctrl->chip); in msm_pinctrl_remove()
1602 unregister_restart_handler(&pctrl->restart_nb); in msm_pinctrl_remove()