Lines Matching +full:edge +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <linux/pinctrl/pinconf-generic.h>
32 #include "../pinctrl-utils.h"
34 #include "pinctrl-msm.h"
41 * struct msm_pinctrl - state for a pinctrl-msm device
52 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
89 return readl(pctrl->regs[g->tile] + g->name##_reg); \
94 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
106 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; in MSM_ACCESSOR()
115 return pctrl->soc->ngroups; in msm_get_groups_count()
123 return pctrl->soc->groups[group].grp.name; in msm_get_group_name()
133 *pins = pctrl->soc->groups[group].grp.pins; in msm_get_group_pins()
134 *num_pins = pctrl->soc->groups[group].grp.npins; in msm_get_group_pins()
146 static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset) in msm_pinmux_request() argument
149 struct gpio_chip *chip = &pctrl->chip; in msm_pinmux_request()
151 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL; in msm_pinmux_request()
158 return pctrl->soc->nfunctions; in msm_get_functions_count()
166 return pctrl->soc->functions[function].name; in msm_get_function_name()
176 *groups = pctrl->soc->functions[function].groups; in msm_get_function_groups()
177 *num_groups = pctrl->soc->functions[function].ngroups; in msm_get_function_groups()
186 struct gpio_chip *gc = &pctrl->chip; in msm_pinmux_set_mux()
187 unsigned int irq = irq_find_mapping(gc->irq.domain, group); in msm_pinmux_set_mux()
189 unsigned int gpio_func = pctrl->soc->gpio_func; in msm_pinmux_set_mux()
190 unsigned int egpio_func = pctrl->soc->egpio_func; in msm_pinmux_set_mux()
196 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
197 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); in msm_pinmux_set_mux()
199 for (i = 0; i < g->nfuncs; i++) { in msm_pinmux_set_mux()
200 if (g->funcs[i] == function) in msm_pinmux_set_mux()
204 if (WARN_ON(i == g->nfuncs)) in msm_pinmux_set_mux()
205 return -EINVAL; in msm_pinmux_set_mux()
218 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux)) in msm_pinmux_set_mux()
221 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_pinmux_set_mux()
231 if (i == gpio_func && (val & BIT(g->oe_bit)) && in msm_pinmux_set_mux()
232 !test_and_set_bit(group, pctrl->ever_gpio)) { in msm_pinmux_set_mux()
235 if (io_val & BIT(g->in_bit)) { in msm_pinmux_set_mux()
236 if (!(io_val & BIT(g->out_bit))) in msm_pinmux_set_mux()
237 msm_writel_io(io_val | BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
239 if (io_val & BIT(g->out_bit)) in msm_pinmux_set_mux()
240 msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
245 if (val & BIT(g->egpio_present)) in msm_pinmux_set_mux()
246 val &= ~BIT(g->egpio_enable); in msm_pinmux_set_mux()
249 val |= i << g->mux_bit; in msm_pinmux_set_mux()
251 if (egpio_func && val & BIT(g->egpio_present)) in msm_pinmux_set_mux()
252 val |= BIT(g->egpio_enable); in msm_pinmux_set_mux()
257 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_pinmux_set_mux()
260 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) { in msm_pinmux_set_mux()
265 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_pinmux_set_mux()
278 unsigned offset) in msm_pinmux_request_gpio() argument
281 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio()
284 if (!g->nfuncs) in msm_pinmux_request_gpio()
287 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset); in msm_pinmux_request_gpio()
310 *bit = g->pull_bit; in msm_config_reg()
312 if (g->i2c_pull_bit) in msm_config_reg()
313 *mask |= BIT(g->i2c_pull_bit) >> *bit; in msm_config_reg()
316 *bit = g->od_bit; in msm_config_reg()
320 *bit = g->drv_bit; in msm_config_reg()
326 *bit = g->oe_bit; in msm_config_reg()
330 return -ENOTSUPP; in msm_config_reg()
362 if (!gpiochip_line_is_valid(&pctrl->chip, group)) in msm_config_group_get()
363 return -EINVAL; in msm_config_group_get()
365 g = &pctrl->soc->groups[group]; in msm_config_group_get()
378 return -EINVAL; in msm_config_group_get()
383 return -EINVAL; in msm_config_group_get()
387 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
388 return -ENOTSUPP; in msm_config_group_get()
391 return -EINVAL; in msm_config_group_get()
395 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
397 else if (arg & BIT(g->i2c_pull_bit)) in msm_config_group_get()
402 return -EINVAL; in msm_config_group_get()
405 /* Pin is not open-drain */ in msm_config_group_get()
407 return -EINVAL; in msm_config_group_get()
416 return -EINVAL; in msm_config_group_get()
419 arg = !!(val & BIT(g->in_bit)); in msm_config_group_get()
423 return -EINVAL; in msm_config_group_get()
426 return -ENOTSUPP; in msm_config_group_get()
450 g = &pctrl->soc->groups[group]; in msm_config_group_set()
469 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
470 return -ENOTSUPP; in msm_config_group_set()
475 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
477 else if (g->i2c_pull_bit && arg == MSM_I2C_STRONG_PULL_UP) in msm_config_group_set()
478 arg = BIT(g->i2c_pull_bit) | MSM_PULL_UP; in msm_config_group_set()
488 arg = -1; in msm_config_group_set()
490 arg = (arg / 2) - 1; in msm_config_group_set()
494 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
497 val |= BIT(g->out_bit); in msm_config_group_set()
499 val &= ~BIT(g->out_bit); in msm_config_group_set()
501 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
509 * actually be a no-op. in msm_config_group_set()
521 * no-op. However, for historical reasons and to in msm_config_group_set()
527 * that "input-enable" and "input-disable" in a device in msm_config_group_set()
538 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", in msm_config_group_set()
540 return -EINVAL; in msm_config_group_set()
543 /* Range-check user-supplied value */ in msm_config_group_set()
545 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); in msm_config_group_set()
546 return -EINVAL; in msm_config_group_set()
549 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
554 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
566 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) in msm_gpio_direction_input() argument
573 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
575 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_input()
578 val &= ~BIT(g->oe_bit); in msm_gpio_direction_input()
581 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_input()
586 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) in msm_gpio_direction_output() argument
593 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
595 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_output()
599 val |= BIT(g->out_bit); in msm_gpio_direction_output()
601 val &= ~BIT(g->out_bit); in msm_gpio_direction_output()
605 val |= BIT(g->oe_bit); in msm_gpio_direction_output()
608 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_output()
613 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) in msm_gpio_get_direction() argument
619 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
623 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT : in msm_gpio_get_direction()
627 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) in msm_gpio_get() argument
633 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
636 return !!(val & BIT(g->in_bit)); in msm_gpio_get()
639 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) in msm_gpio_set() argument
646 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
648 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_set()
652 val |= BIT(g->out_bit); in msm_gpio_set()
654 val &= ~BIT(g->out_bit); in msm_gpio_set()
657 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_set()
665 unsigned offset, in msm_gpio_dbg_show_one() argument
691 if (!gpiochip_line_is_valid(chip, offset)) in msm_gpio_dbg_show_one()
694 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
698 is_out = !!(ctl_reg & BIT(g->oe_bit)); in msm_gpio_dbg_show_one()
699 func = (ctl_reg >> g->mux_bit) & 7; in msm_gpio_dbg_show_one()
700 drive = (ctl_reg >> g->drv_bit) & 7; in msm_gpio_dbg_show_one()
701 pull = (ctl_reg >> g->pull_bit) & 3; in msm_gpio_dbg_show_one()
703 if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present)) in msm_gpio_dbg_show_one()
704 egpio_enable = !(ctl_reg & BIT(g->egpio_enable)); in msm_gpio_dbg_show_one()
707 val = !!(io_reg & BIT(g->out_bit)); in msm_gpio_dbg_show_one()
709 val = !!(io_reg & BIT(g->in_bit)); in msm_gpio_dbg_show_one()
712 seq_printf(s, " %-8s: egpio\n", g->grp.name); in msm_gpio_dbg_show_one()
716 seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in"); in msm_gpio_dbg_show_one()
717 seq_printf(s, " %-4s func%d", val ? "high" : "low", func); in msm_gpio_dbg_show_one()
719 if (pctrl->soc->pull_no_keeper) in msm_gpio_dbg_show_one()
728 unsigned gpio = chip->base; in msm_gpio_dbg_show()
731 for (i = 0; i < chip->ngpio; i++, gpio++) in msm_gpio_dbg_show()
746 const int *reserved = pctrl->soc->reserved_gpios; in msm_gpio_init_valid_mask()
749 /* Remove driver-provided reserved GPIOs from valid_mask */ in msm_gpio_init_valid_mask()
753 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); in msm_gpio_init_valid_mask()
754 return -EINVAL; in msm_gpio_init_valid_mask()
763 len = ret = device_property_count_u16(pctrl->dev, "gpios"); in msm_gpio_init_valid_mask()
768 return -EINVAL; in msm_gpio_init_valid_mask()
772 return -ENOMEM; in msm_gpio_init_valid_mask()
774 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); in msm_gpio_init_valid_mask()
776 dev_err(pctrl->dev, "could not read list of GPIOs\n"); in msm_gpio_init_valid_mask()
800 /* For dual-edge interrupts in software, since some hardware has no
804 * settings of both-edge irq lines to try and catch the next edge.
807 * - the status bit goes high, indicating that an edge was caught, or
808 * - the input value of the gpio doesn't change during the attempt.
813 * The do-loop tries to sledge-hammer closed the timing hole between
814 * the initial value-read and the polarity-write - if the line value changes
829 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
832 pol ^= BIT(g->intr_polarity_bit); in msm_gpio_update_dual_edge_pos()
835 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
839 } while (loop_limit-- > 0); in msm_gpio_update_dual_edge_pos()
840 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", in msm_gpio_update_dual_edge_pos()
852 if (d->parent_data) in msm_gpio_irq_mask()
855 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_mask()
858 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
860 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_mask()
865 * RAW_STATUS_EN bit causes the level or edge sensed on the line to be in msm_gpio_irq_mask()
867 * an irq that it's configured for (either edge for edge type or level in msm_gpio_irq_mask()
868 * for level type irq). The 'non-raw' status enable bit causes the in msm_gpio_irq_mask()
870 * status bit is set. There's a bug though, the edge detection logic in msm_gpio_irq_mask()
872 * cause the status bit to latch spuriously when there isn't any edge in msm_gpio_irq_mask()
873 * so we can't touch that bit for edge type irqs and we have to keep in msm_gpio_irq_mask()
877 * enabled all the time causes level interrupts to re-latch into the in msm_gpio_irq_mask()
884 val &= ~BIT(g->intr_raw_status_bit); in msm_gpio_irq_mask()
886 val &= ~BIT(g->intr_enable_bit); in msm_gpio_irq_mask()
889 clear_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_mask()
891 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_mask()
902 if (d->parent_data) in msm_gpio_irq_unmask()
905 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_unmask()
908 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
910 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_unmask()
913 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_unmask()
914 val |= BIT(g->intr_enable_bit); in msm_gpio_irq_unmask()
917 set_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_unmask()
919 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_unmask()
927 gpiochip_enable_irq(gc, d->hwirq); in msm_gpio_irq_enable()
929 if (d->parent_data) in msm_gpio_irq_enable()
932 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_enable()
941 if (d->parent_data) in msm_gpio_irq_disable()
944 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_disable()
947 gpiochip_disable_irq(gc, d->hwirq); in msm_gpio_irq_disable()
951 * msm_gpio_update_dual_edge_parent() - Prime next edge for IRQs handled by parent.
963 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_update_dual_edge_parent()
968 /* Read the value and make a guess about what edge we need to catch */ in msm_gpio_update_dual_edge_parent()
969 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
973 /* Set the parent to catch the next edge */ in msm_gpio_update_dual_edge_parent()
978 * (and decided what edge we needed) and when set the edge. in msm_gpio_update_dual_edge_parent()
982 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
992 } while (loop_limit-- > 0); in msm_gpio_update_dual_edge_parent()
993 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n"); in msm_gpio_update_dual_edge_parent()
1003 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_ack()
1004 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
1009 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
1011 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_ack()
1015 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
1018 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_ack()
1023 d = d->parent_data; in msm_gpio_irq_eoi()
1026 d->chip->irq_eoi(d); in msm_gpio_irq_eoi()
1036 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data && in msm_gpio_needs_dual_edge_parent_workaround()
1037 test_bit(d->hwirq, pctrl->skip_wake_irqs); in msm_gpio_needs_dual_edge_parent_workaround()
1051 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1057 if (d->parent_data) in msm_gpio_irq_set_type()
1060 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_set_type()
1061 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1066 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
1068 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1073 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) in msm_gpio_irq_set_type()
1074 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1076 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1082 if (g->intr_target_width) in msm_gpio_irq_set_type()
1083 intr_target_mask = GENMASK(g->intr_target_width - 1, 0); in msm_gpio_irq_set_type()
1085 if (pctrl->intr_target_use_scm) { in msm_gpio_irq_set_type()
1086 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; in msm_gpio_irq_set_type()
1090 val &= ~(intr_target_mask << g->intr_target_bit); in msm_gpio_irq_set_type()
1091 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1095 dev_err(pctrl->dev, in msm_gpio_irq_set_type()
1097 d->hwirq); in msm_gpio_irq_set_type()
1100 val &= ~(intr_target_mask << g->intr_target_bit); in msm_gpio_irq_set_type()
1101 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1108 * could cause the INTR_STATUS to be set for EDGE interrupts. in msm_gpio_irq_set_type()
1111 was_enabled = val & BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
1112 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
1113 if (g->intr_detection_width == 2) { in msm_gpio_irq_set_type()
1114 val &= ~(3 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1115 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1118 val |= 1 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1119 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1122 val |= 2 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1123 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1126 val |= 3 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1127 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1132 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1135 } else if (g->intr_detection_width == 1) { in msm_gpio_irq_set_type()
1136 val &= ~(1 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1137 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1140 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1141 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1144 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1147 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1148 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1153 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1169 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_set_type()
1172 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1193 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_wake()
1196 return irq_set_irq_wake(pctrl->irq, on); in msm_gpio_irq_set_wake()
1203 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_reqres()
1207 if (!try_module_get(gc->owner)) in msm_gpio_irq_reqres()
1208 return -ENODEV; in msm_gpio_irq_reqres()
1210 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); in msm_gpio_irq_reqres()
1213 msm_gpio_direction_input(gc, d->hwirq); in msm_gpio_irq_reqres()
1215 if (gpiochip_lock_as_irq(gc, d->hwirq)) { in msm_gpio_irq_reqres()
1216 dev_err(gc->parent, in msm_gpio_irq_reqres()
1218 d->hwirq); in msm_gpio_irq_reqres()
1219 ret = -EINVAL; in msm_gpio_irq_reqres()
1224 * The disable / clear-enable workaround we do in msm_pinmux_set_mux() in msm_gpio_irq_reqres()
1228 irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY); in msm_gpio_irq_reqres()
1238 if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { in msm_gpio_irq_reqres()
1241 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_reqres()
1244 if (intr_cfg & BIT(g->intr_wakeup_present_bit)) { in msm_gpio_irq_reqres()
1245 intr_cfg |= BIT(g->intr_wakeup_enable_bit); in msm_gpio_irq_reqres()
1249 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_reqres()
1254 module_put(gc->owner); in msm_gpio_irq_reqres()
1262 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_relres()
1266 if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { in msm_gpio_irq_relres()
1269 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_relres()
1272 if (intr_cfg & BIT(g->intr_wakeup_present_bit)) { in msm_gpio_irq_relres()
1273 intr_cfg &= ~BIT(g->intr_wakeup_enable_bit); in msm_gpio_irq_relres()
1277 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_relres()
1280 gpiochip_unlock_as_irq(gc, d->hwirq); in msm_gpio_irq_relres()
1281 module_put(gc->owner); in msm_gpio_irq_relres()
1290 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_affinity()
1293 return -EINVAL; in msm_gpio_irq_set_affinity()
1301 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_vcpu_affinity()
1304 return -EINVAL; in msm_gpio_irq_set_vcpu_affinity()
1323 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { in msm_gpio_irq_handler()
1324 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
1326 if (val & BIT(g->intr_status_bit)) { in msm_gpio_irq_handler()
1327 generic_handle_domain_irq(gc->irq.domain, i); in msm_gpio_irq_handler()
1352 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_wakeirq()
1353 map = &pctrl->soc->wakeirq_map[i]; in msm_gpio_wakeirq()
1354 if (map->gpio == child) { in msm_gpio_wakeirq()
1355 *parent = map->wakeirq; in msm_gpio_wakeirq()
1365 if (pctrl->soc->reserved_gpios) in msm_gpio_needs_valid_mask()
1368 return device_property_count_u16(pctrl->dev, "gpios") > 0; in msm_gpio_needs_valid_mask()
1396 unsigned gpio, ngpio = pctrl->soc->ngpios; in msm_gpio_init()
1401 return -EINVAL; in msm_gpio_init()
1403 chip = &pctrl->chip; in msm_gpio_init()
1404 chip->base = -1; in msm_gpio_init()
1405 chip->ngpio = ngpio; in msm_gpio_init()
1406 chip->label = dev_name(pctrl->dev); in msm_gpio_init()
1407 chip->parent = pctrl->dev; in msm_gpio_init()
1408 chip->owner = THIS_MODULE; in msm_gpio_init()
1410 chip->init_valid_mask = msm_gpio_init_valid_mask; in msm_gpio_init()
1412 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); in msm_gpio_init()
1414 chip->irq.parent_domain = irq_find_matching_host(np, in msm_gpio_init()
1417 if (!chip->irq.parent_domain) in msm_gpio_init()
1418 return -EPROBE_DEFER; in msm_gpio_init()
1419 chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq; in msm_gpio_init()
1424 skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain); in msm_gpio_init()
1425 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_init()
1426 gpio = pctrl->soc->wakeirq_map[i].gpio; in msm_gpio_init()
1427 set_bit(gpio, pctrl->skip_wake_irqs); in msm_gpio_init()
1431 girq = &chip->irq; in msm_gpio_init()
1433 girq->parent_handler = msm_gpio_irq_handler; in msm_gpio_init()
1434 girq->fwnode = dev_fwnode(pctrl->dev); in msm_gpio_init()
1435 girq->num_parents = 1; in msm_gpio_init()
1436 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), in msm_gpio_init()
1438 if (!girq->parents) in msm_gpio_init()
1439 return -ENOMEM; in msm_gpio_init()
1440 girq->default_type = IRQ_TYPE_NONE; in msm_gpio_init()
1441 girq->handler = handle_bad_irq; in msm_gpio_init()
1442 girq->parents[0] = pctrl->irq; in msm_gpio_init()
1444 ret = gpiochip_add_data(&pctrl->chip, pctrl); in msm_gpio_init()
1446 dev_err(pctrl->dev, "Failed register gpiochip\n"); in msm_gpio_init()
1451 * For DeviceTree-supported systems, the gpio core checks the in msm_gpio_init()
1452 * pinctrl's device node for the "gpio-ranges" property. in msm_gpio_init()
1457 * files which don't set the "gpio-ranges" property or systems that in msm_gpio_init()
1460 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { in msm_gpio_init()
1461 ret = gpiochip_add_pin_range(&pctrl->chip, in msm_gpio_init()
1462 dev_name(pctrl->dev), 0, 0, chip->ngpio); in msm_gpio_init()
1464 dev_err(pctrl->dev, "Failed to add pin range\n"); in msm_gpio_init()
1465 gpiochip_remove(&pctrl->chip); in msm_gpio_init()
1478 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); in msm_ps_hold_restart()
1487 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); in msm_ps_hold_poweroff()
1493 const struct pinfunction *func = pctrl->soc->functions; in msm_pinctrl_setup_pm_reset()
1495 for (i = 0; i < pctrl->soc->nfunctions; i++) in msm_pinctrl_setup_pm_reset()
1497 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; in msm_pinctrl_setup_pm_reset()
1498 pctrl->restart_nb.priority = 128; in msm_pinctrl_setup_pm_reset()
1499 if (register_restart_handler(&pctrl->restart_nb)) in msm_pinctrl_setup_pm_reset()
1500 dev_err(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1512 return pinctrl_force_sleep(pctrl->pctrl); in msm_pinctrl_suspend()
1519 return pinctrl_force_default(pctrl->pctrl); in msm_pinctrl_resume()
1535 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in msm_pinctrl_probe()
1537 return -ENOMEM; in msm_pinctrl_probe()
1539 pctrl->dev = &pdev->dev; in msm_pinctrl_probe()
1540 pctrl->soc = soc_data; in msm_pinctrl_probe()
1541 pctrl->chip = msm_gpio_template; in msm_pinctrl_probe()
1542 pctrl->intr_target_use_scm = of_device_is_compatible( in msm_pinctrl_probe()
1543 pctrl->dev->of_node, in msm_pinctrl_probe()
1544 "qcom,ipq8064-pinctrl"); in msm_pinctrl_probe()
1546 raw_spin_lock_init(&pctrl->lock); in msm_pinctrl_probe()
1548 if (soc_data->tiles) { in msm_pinctrl_probe()
1549 for (i = 0; i < soc_data->ntiles; i++) { in msm_pinctrl_probe()
1551 soc_data->tiles[i]); in msm_pinctrl_probe()
1552 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1553 if (IS_ERR(pctrl->regs[i])) in msm_pinctrl_probe()
1554 return PTR_ERR(pctrl->regs[i]); in msm_pinctrl_probe()
1557 pctrl->regs[0] = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in msm_pinctrl_probe()
1558 if (IS_ERR(pctrl->regs[0])) in msm_pinctrl_probe()
1559 return PTR_ERR(pctrl->regs[0]); in msm_pinctrl_probe()
1561 pctrl->phys_base[0] = res->start; in msm_pinctrl_probe()
1566 pctrl->irq = platform_get_irq(pdev, 0); in msm_pinctrl_probe()
1567 if (pctrl->irq < 0) in msm_pinctrl_probe()
1568 return pctrl->irq; in msm_pinctrl_probe()
1570 pctrl->desc.owner = THIS_MODULE; in msm_pinctrl_probe()
1571 pctrl->desc.pctlops = &msm_pinctrl_ops; in msm_pinctrl_probe()
1572 pctrl->desc.pmxops = &msm_pinmux_ops; in msm_pinctrl_probe()
1573 pctrl->desc.confops = &msm_pinconf_ops; in msm_pinctrl_probe()
1574 pctrl->desc.name = dev_name(&pdev->dev); in msm_pinctrl_probe()
1575 pctrl->desc.pins = pctrl->soc->pins; in msm_pinctrl_probe()
1576 pctrl->desc.npins = pctrl->soc->npins; in msm_pinctrl_probe()
1578 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in msm_pinctrl_probe()
1579 if (IS_ERR(pctrl->pctrl)) { in msm_pinctrl_probe()
1580 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); in msm_pinctrl_probe()
1581 return PTR_ERR(pctrl->pctrl); in msm_pinctrl_probe()
1590 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); in msm_pinctrl_probe()
1600 gpiochip_remove(&pctrl->chip); in msm_pinctrl_remove()
1602 unregister_restart_handler(&pctrl->restart_nb); in msm_pinctrl_remove()