Lines Matching +full:spi +full:- +full:nand
1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinmux-xway.c
4 * based on linux/drivers/pinctrl/pinmux-pxa910.c
21 #include "pinctrl-lantiq.h"
110 /* --------- ase related code --------- */
122 MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG),
123 MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG),
124 MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG),
125 MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG),
129 MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU),
130 MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO),
186 GRP_MUX("spi", SPI, ase_pins_spi), /* DEPRECATED */
187 GRP_MUX("spi_di", SPI, ase_pins_spi_di),
188 GRP_MUX("spi_do", SPI, ase_pins_spi_do),
189 GRP_MUX("spi_clk", SPI, ase_pins_spi_clk),
190 GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1),
191 GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2),
192 GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3),
220 static const char * const ase_spi_grps[] = {"spi", /* DEPRECATED */
226 {"spi", ARRAY_AND_SIZE(ase_spi_grps)},
238 /* --------- danube related code --------- */
252 MFP_XWAY(GPIO9, GPIO, ASC, SPI, MII),
253 MFP_XWAY(GPIO10, GPIO, ASC, SPI, MII),
254 MFP_XWAY(GPIO11, GPIO, ASC, CBUS, SPI),
256 MFP_XWAY(GPIO13, GPIO, EBU, SPI, MII),
258 MFP_XWAY(GPIO15, GPIO, SPI, SDIO, JTAG),
259 MFP_XWAY(GPIO16, GPIO, SPI, SDIO, JTAG),
260 MFP_XWAY(GPIO17, GPIO, SPI, SDIO, JTAG),
261 MFP_XWAY(GPIO18, GPIO, SPI, SDIO, JTAG),
265 MFP_XWAY(GPIO22, GPIO, SPI, MCD, MII),
341 GRP_MUX("nand ale", EBU, danube_pins_nand_ale),
342 GRP_MUX("nand cs1", EBU, danube_pins_nand_cs1),
343 GRP_MUX("nand cle", EBU, danube_pins_nand_cle),
344 GRP_MUX("spi", SPI, danube_pins_spi), /* DEPRECATED */
345 GRP_MUX("spi_di", SPI, danube_pins_spi_di),
346 GRP_MUX("spi_do", SPI, danube_pins_spi_do),
347 GRP_MUX("spi_clk", SPI, danube_pins_spi_clk),
348 GRP_MUX("spi_cs1", SPI, danube_pins_spi_cs1),
349 GRP_MUX("spi_cs2", SPI, danube_pins_spi_cs2),
350 GRP_MUX("spi_cs3", SPI, danube_pins_spi_cs3),
351 GRP_MUX("spi_cs4", SPI, danube_pins_spi_cs4),
352 GRP_MUX("spi_cs5", SPI, danube_pins_spi_cs5),
353 GRP_MUX("spi_cs6", SPI, danube_pins_spi_cs6),
378 static const char * const danube_spi_grps[] = {"spi", /* DEPRECATED */
389 "nand ale", "nand cs1",
390 "nand cle"};
400 {"spi", ARRAY_AND_SIZE(danube_spi_grps)},
413 /* --------- xrx100 related code --------- */
427 MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN),
428 MFP_XWAY(GPIO10, GPIO, ASC, SPI, EXIN),
429 MFP_XWAY(GPIO11, GPIO, ASC, CBUS, SPI),
431 MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
433 MFP_XWAY(GPIO15, GPIO, SPI, SDIO, MCD),
434 MFP_XWAY(GPIO16, GPIO, SPI, SDIO, NONE),
435 MFP_XWAY(GPIO17, GPIO, SPI, SDIO, NONE),
436 MFP_XWAY(GPIO18, GPIO, SPI, SDIO, NONE),
440 MFP_XWAY(GPIO22, GPIO, SPI, NONE, EBU),
548 GRP_MUX("nand ale", EBU, xrx100_pins_nand_ale),
549 GRP_MUX("nand cs1", EBU, xrx100_pins_nand_cs1),
550 GRP_MUX("nand cle", EBU, xrx100_pins_nand_cle),
551 GRP_MUX("nand rdy", EBU, xrx100_pins_nand_rdy),
552 GRP_MUX("nand rd", EBU, xrx100_pins_nand_rd),
553 GRP_MUX("spi_di", SPI, xrx100_pins_spi_di),
554 GRP_MUX("spi_do", SPI, xrx100_pins_spi_do),
555 GRP_MUX("spi_clk", SPI, xrx100_pins_spi_clk),
556 GRP_MUX("spi_cs1", SPI, xrx100_pins_spi_cs1),
557 GRP_MUX("spi_cs2", SPI, xrx100_pins_spi_cs2),
558 GRP_MUX("spi_cs3", SPI, xrx100_pins_spi_cs3),
559 GRP_MUX("spi_cs4", SPI, xrx100_pins_spi_cs4),
560 GRP_MUX("spi_cs5", SPI, xrx100_pins_spi_cs5),
561 GRP_MUX("spi_cs6", SPI, xrx100_pins_spi_cs6),
600 "nand ale", "nand cs1",
601 "nand cle", "nand rdy",
602 "nand rd"};
613 {"spi", ARRAY_AND_SIZE(xrx100_spi_grps)},
626 /* --------- xrx200 related code --------- */
640 MFP_XWAY(GPIO9, GPIO, USIF, SPI, EXIN),
641 MFP_XWAY(GPIO10, GPIO, USIF, SPI, EXIN),
642 MFP_XWAY(GPIO11, GPIO, USIF, CBUS, SPI),
644 MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
646 MFP_XWAY(GPIO15, GPIO, SPI, SDIO, MCD),
647 MFP_XWAY(GPIO16, GPIO, SPI, SDIO, NONE),
648 MFP_XWAY(GPIO17, GPIO, SPI, SDIO, NONE),
649 MFP_XWAY(GPIO18, GPIO, SPI, SDIO, NONE),
653 MFP_XWAY(GPIO22, GPIO, SPI, CGU, EBU),
776 GRP_MUX("nand ale", EBU, xrx200_pins_nand_ale),
777 GRP_MUX("nand cs1", EBU, xrx200_pins_nand_cs1),
778 GRP_MUX("nand cle", EBU, xrx200_pins_nand_cle),
779 GRP_MUX("nand rdy", EBU, xrx200_pins_nand_rdy),
780 GRP_MUX("nand rd", EBU, xrx200_pins_nand_rd),
781 GRP_MUX("spi_di", SPI, xrx200_pins_spi_di),
782 GRP_MUX("spi_do", SPI, xrx200_pins_spi_do),
783 GRP_MUX("spi_clk", SPI, xrx200_pins_spi_clk),
784 GRP_MUX("spi_cs1", SPI, xrx200_pins_spi_cs1),
785 GRP_MUX("spi_cs2", SPI, xrx200_pins_spi_cs2),
786 GRP_MUX("spi_cs3", SPI, xrx200_pins_spi_cs3),
787 GRP_MUX("spi_cs4", SPI, xrx200_pins_spi_cs4),
788 GRP_MUX("spi_cs5", SPI, xrx200_pins_spi_cs5),
789 GRP_MUX("spi_cs6", SPI, xrx200_pins_spi_cs6),
846 "nand ale", "nand cs1",
847 "nand cle", "nand rdy",
848 "nand rd"};
868 {"spi", ARRAY_AND_SIZE(xrx200_spi_grps)},
882 /* --------- xrx300 related code --------- */
897 MFP_XWAY(GPIO10, GPIO, USIF, SPI, EXIN),
898 MFP_XWAY(GPIO11, GPIO, USIF, WIFI, SPI),
902 MFP_XWAY(GPIO15, GPIO, SPI, NONE, MCD),
903 MFP_XWAY(GPIO16, GPIO, SPI, EXIN, NONE),
904 MFP_XWAY(GPIO17, GPIO, SPI, NONE, NONE),
905 MFP_XWAY(GPIO18, GPIO, SPI, NONE, NONE),
1019 GRP_MUX("nand ale", EBU, xrx300_pins_nand_ale),
1020 GRP_MUX("nand cs1", EBU, xrx300_pins_nand_cs1),
1021 GRP_MUX("nand cle", EBU, xrx300_pins_nand_cle),
1022 GRP_MUX("nand rdy", EBU, xrx300_pins_nand_rdy),
1023 GRP_MUX("nand rd", EBU, xrx300_pins_nand_rd),
1024 GRP_MUX("nand d1", EBU, xrx300_pins_nand_d1),
1025 GRP_MUX("nand d0", EBU, xrx300_pins_nand_d0),
1026 GRP_MUX("nand d2", EBU, xrx300_pins_nand_d2),
1027 GRP_MUX("nand d7", EBU, xrx300_pins_nand_d7),
1028 GRP_MUX("nand d6", EBU, xrx300_pins_nand_d6),
1029 GRP_MUX("nand d5", EBU, xrx300_pins_nand_d5),
1030 GRP_MUX("nand d4", EBU, xrx300_pins_nand_d4),
1031 GRP_MUX("nand d3", EBU, xrx300_pins_nand_d3),
1032 GRP_MUX("nand cs0", EBU, xrx300_pins_nand_cs0),
1033 GRP_MUX("nand wr", EBU, xrx300_pins_nand_wr),
1034 GRP_MUX("nand wp", EBU, xrx300_pins_nand_wp),
1035 GRP_MUX("nand se", EBU, xrx300_pins_nand_se),
1036 GRP_MUX("spi_di", SPI, xrx300_pins_spi_di),
1037 GRP_MUX("spi_do", SPI, xrx300_pins_spi_do),
1038 GRP_MUX("spi_clk", SPI, xrx300_pins_spi_clk),
1039 GRP_MUX("spi_cs1", SPI, xrx300_pins_spi_cs1),
1040 GRP_MUX("spi_cs4", SPI, xrx300_pins_spi_cs4),
1041 GRP_MUX("spi_cs6", SPI, xrx300_pins_spi_cs6),
1063 static const char * const xrx300_ebu_grps[] = {"nand ale", "nand cs1",
1064 "nand cle", "nand rdy",
1065 "nand rd", "nand d1",
1066 "nand d0", "nand d2",
1067 "nand d7", "nand d6",
1068 "nand d5", "nand d4",
1069 "nand d3", "nand cs0",
1070 "nand wr", "nand wp",
1071 "nand se"};
1084 {"spi", ARRAY_AND_SIZE(xrx300_spi_grps)},
1095 /* --------- pinconf related code --------- */
1112 !gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); in xway_pinconf_get()
1120 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) { in xway_pinconf_get()
1129 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) in xway_pinconf_get()
1138 gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); in xway_pinconf_get()
1141 dev_err(pctldev->dev, "Invalid config param %04x\n", param); in xway_pinconf_get()
1142 return -ENOTSUPP; in xway_pinconf_get()
1170 gpio_setbit(info->membase[0], in xway_pinconf_set()
1174 gpio_clearbit(info->membase[0], in xway_pinconf_set()
1185 gpio_clearbit(info->membase[0], in xway_pinconf_set()
1190 gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); in xway_pinconf_set()
1197 gpio_clearbit(info->membase[0], in xway_pinconf_set()
1201 gpio_setbit(info->membase[0], in xway_pinconf_set()
1205 dev_err(pctldev->dev, in xway_pinconf_set()
1212 gpio_clearbit(info->membase[0], in xway_pinconf_set()
1216 gpio_setbit(info->membase[0], in xway_pinconf_set()
1222 dev_err(pctldev->dev, in xway_pinconf_set()
1224 return -ENOTSUPP; in xway_pinconf_set()
1239 for (i = 0; i < info->grps[selector].npins && !ret; i++) in xway_pinconf_group_set()
1241 info->grps[selector].pins[i], in xway_pinconf_group_set()
1270 gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); in xway_mux_apply()
1272 gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); in xway_mux_apply()
1275 gpio_setbit(info->membase[0], alt1_reg, PORT_PIN(pin)); in xway_mux_apply()
1277 gpio_clearbit(info->membase[0], alt1_reg, PORT_PIN(pin)); in xway_mux_apply()
1284 {"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN},
1295 /* --------- gpio_chip related code --------- */
1298 struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent); in xway_gpio_set()
1301 gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); in xway_gpio_set()
1303 gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); in xway_gpio_set()
1308 struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent); in xway_gpio_get()
1310 return !!gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin)); in xway_gpio_get()
1315 struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent); in xway_gpio_dir_in()
1317 gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); in xway_gpio_dir_in()
1324 struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent); in xway_gpio_dir_out()
1327 gpio_setbit(info->membase[0], GPIO3_OD, PORT_PIN(pin)); in xway_gpio_dir_out()
1329 gpio_setbit(info->membase[0], GPIO_OD(pin), PORT_PIN(pin)); in xway_gpio_dir_out()
1330 gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); in xway_gpio_dir_out()
1342 struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent); in xway_gpio_to_irq()
1345 for (i = 0; i < info->num_exin; i++) in xway_gpio_to_irq()
1346 if (info->exin[i] == offset) in xway_gpio_to_irq()
1349 return -1; in xway_gpio_to_irq()
1353 .label = "gpio-xway",
1361 .base = -1,
1365 /* --------- register the pinctrl layer --------- */
1443 { .compatible = "lantiq,ase-pinctrl", .data = &ase_pinctrl},
1444 { .compatible = "lantiq,danube-pinctrl", .data = &danube_pinctrl},
1445 { .compatible = "lantiq,xrx100-pinctrl", .data = &xrx100_pinctrl},
1446 { .compatible = "lantiq,xrx200-pinctrl", .data = &xrx200_pinctrl},
1447 { .compatible = "lantiq,xrx300-pinctrl", .data = &xrx300_pinctrl},
1462 xway_soc = device_get_match_data(&pdev->dev); in pinmux_xway_probe()
1467 xway_chip.ngpio = xway_soc->pin_count; in pinmux_xway_probe()
1470 xway_info.pads = devm_kcalloc(&pdev->dev, in pinmux_xway_probe()
1474 return -ENOMEM; in pinmux_xway_probe()
1477 char *name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "io%d", i); in pinmux_xway_probe()
1480 return -ENOMEM; in pinmux_xway_probe()
1488 xway_pctrl_desc.name = dev_name(&pdev->dev); in pinmux_xway_probe()
1493 xway_info.mfp = xway_soc->mfp; in pinmux_xway_probe()
1494 xway_info.grps = xway_soc->grps; in pinmux_xway_probe()
1495 xway_info.num_grps = xway_soc->num_grps; in pinmux_xway_probe()
1496 xway_info.funcs = xway_soc->funcs; in pinmux_xway_probe()
1497 xway_info.num_funcs = xway_soc->num_funcs; in pinmux_xway_probe()
1498 xway_info.exin = xway_soc->exin; in pinmux_xway_probe()
1499 xway_info.num_exin = xway_soc->num_exin; in pinmux_xway_probe()
1504 dev_err(&pdev->dev, "Failed to register pinctrl driver\n"); in pinmux_xway_probe()
1509 xway_chip.parent = &pdev->dev; in pinmux_xway_probe()
1511 ret = devm_gpiochip_add_data(&pdev->dev, &xway_chip, NULL); in pinmux_xway_probe()
1513 dev_err(&pdev->dev, "Failed to register gpio chip\n"); in pinmux_xway_probe()
1518 * For DeviceTree-supported systems, the gpio core checks the in pinmux_xway_probe()
1519 * pinctrl's device node for the "gpio-ranges" property. in pinmux_xway_probe()
1524 * files which don't set the "gpio-ranges" property or systems that in pinmux_xway_probe()
1527 if (!of_property_read_bool(pdev->dev.of_node, "gpio-ranges")) { in pinmux_xway_probe()
1534 dev_info(&pdev->dev, "Init done\n"); in pinmux_xway_probe()
1541 .name = "pinctrl-xway",