Lines Matching +full:bit +full:- +full:per +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
30 #include <linux/pinctrl/pinconf-generic.h>
37 #include <dt-bindings/pinctrl/rockchip.h>
41 #include "pinctrl-rockchip.h"
44 * Generate a bitmask for setting a value (v) with a write mask bit in hiword
53 #define IOMUX_GPIO_ONLY BIT(0)
54 #define IOMUX_WIDTH_4BIT BIT(1)
55 #define IOMUX_SOURCE_PMU BIT(2)
56 #define IOMUX_UNROUTED BIT(3)
57 #define IOMUX_WIDTH_3BIT BIT(4)
58 #define IOMUX_WIDTH_2BIT BIT(5)
59 #define IOMUX_L_SOURCE_PMU BIT(6)
67 { .offset = -1 }, \
68 { .offset = -1 }, \
69 { .offset = -1 }, \
70 { .offset = -1 }, \
80 { .type = iom0, .offset = -1 }, \
81 { .type = iom1, .offset = -1 }, \
82 { .type = iom2, .offset = -1 }, \
83 { .type = iom3, .offset = -1 }, \
114 { .offset = -1 }, \
115 { .offset = -1 }, \
116 { .offset = -1 }, \
117 { .offset = -1 }, \
120 { .drv_type = type0, .offset = -1 }, \
121 { .drv_type = type1, .offset = -1 }, \
122 { .drv_type = type2, .offset = -1 }, \
123 { .drv_type = type3, .offset = -1 }, \
135 { .type = iom0, .offset = -1 }, \
136 { .type = iom1, .offset = -1 }, \
137 { .type = iom2, .offset = -1 }, \
138 { .type = iom3, .offset = -1 }, \
154 { .offset = -1 }, \
155 { .offset = -1 }, \
156 { .offset = -1 }, \
157 { .offset = -1 }, \
160 { .drv_type = drv0, .offset = -1 }, \
161 { .drv_type = drv1, .offset = -1 }, \
162 { .drv_type = drv2, .offset = -1 }, \
163 { .drv_type = drv3, .offset = -1 }, \
195 { .type = iom0, .offset = -1 }, \
196 { .type = iom1, .offset = -1 }, \
197 { .type = iom2, .offset = -1 }, \
198 { .type = iom3, .offset = -1 }, \
219 { .type = iom0, .offset = -1 }, \
220 { .type = iom1, .offset = -1 }, \
221 { .type = iom2, .offset = -1 }, \
222 { .type = iom3, .offset = -1 }, \
270 for (i = 0; i < info->ngroups; i++) { in pinctrl_name_to_group()
271 if (!strcmp(info->groups[i].name, name)) in pinctrl_name_to_group()
272 return &info->groups[i]; in pinctrl_name_to_group()
285 struct rockchip_pin_bank *b = info->ctrl->pin_banks; in pin_to_bank()
287 while (pin >= (b->pin_base + b->nr_pins)) in pin_to_bank()
297 struct rockchip_pin_bank *b = info->ctrl->pin_banks; in bank_num_to_bank()
300 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { in bank_num_to_bank()
301 if (b->bank_num == num) in bank_num_to_bank()
305 return ERR_PTR(-EINVAL); in bank_num_to_bank()
316 return info->ngroups; in rockchip_get_groups_count()
324 return info->groups[selector].name; in rockchip_get_group_name()
333 if (selector >= info->ngroups) in rockchip_get_group_pins()
334 return -EINVAL; in rockchip_get_group_pins()
336 *pins = info->groups[selector].pins; in rockchip_get_group_pins()
337 *npins = info->groups[selector].npins; in rockchip_get_group_pins()
348 struct device *dev = info->dev; in rockchip_dt_node_to_map()
358 grp = pinctrl_name_to_group(info, np->name); in rockchip_dt_node_to_map()
361 return -EINVAL; in rockchip_dt_node_to_map()
364 map_num += grp->npins; in rockchip_dt_node_to_map()
368 return -ENOMEM; in rockchip_dt_node_to_map()
373 /* create mux map */ in rockchip_dt_node_to_map()
377 return -EINVAL; in rockchip_dt_node_to_map()
380 new_map[0].data.mux.function = parent->name; in rockchip_dt_node_to_map()
381 new_map[0].data.mux.group = np->name; in rockchip_dt_node_to_map()
386 for (i = 0; i < grp->npins; i++) { in rockchip_dt_node_to_map()
389 pin_get_name(pctldev, grp->pins[i]); in rockchip_dt_node_to_map()
390 new_map[i].data.configs.configs = grp->data[i].configs; in rockchip_dt_node_to_map()
391 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; in rockchip_dt_node_to_map()
395 (*map)->data.mux.function, (*map)->data.mux.group, map_num); in rockchip_dt_node_to_map()
423 .bit = 0,
429 .bit = 2,
435 .bit = 4,
441 .bit = 6,
447 .bit = 8,
453 .bit = 10,
459 .bit = 12,
465 .bit = 14,
471 .bit = 0,
477 .bit = 2,
487 .bit = 0,
494 .bit = 4,
501 .bit = 8,
508 .bit = 12,
518 .bit = 0,
524 .bit = 4,
530 .bit = 8,
536 .bit = 12,
542 .bit = 12,
553 .bit = 12,
560 .bit = 0,
567 .bit = 4,
574 .bit = 8,
581 .bit = 12,
588 .bit = 0,
595 .bit = 4,
602 .bit = 8,
609 .bit = 4,
616 .bit = 6,
623 .bit = 0,
630 .bit = 4,
637 .bit = 6,
644 .bit = 8,
651 .bit = 12,
662 .bit = 0,
669 .bit = 14,
676 .bit = 2,
683 .bit = 4,
690 .bit = 6,
697 .bit = 8,
704 .bit = 10,
711 .bit = 12,
718 .bit = 14,
724 int *reg, u8 *bit, int *mask) in rockchip_get_recalced_mux() argument
726 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
727 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_recalced_mux()
731 for (i = 0; i < ctrl->niomux_recalced; i++) { in rockchip_get_recalced_mux()
732 data = &ctrl->iomux_recalced[i]; in rockchip_get_recalced_mux()
733 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
734 data->pin == pin) in rockchip_get_recalced_mux()
738 if (i >= ctrl->niomux_recalced) in rockchip_get_recalced_mux()
741 *reg = data->reg; in rockchip_get_recalced_mux()
742 *mask = data->mask; in rockchip_get_recalced_mux()
743 *bit = data->bit; in rockchip_get_recalced_mux()
747 RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */
748 RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */
749 RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */
750 RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */
751 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
752 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
753 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */
754 RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */
755 RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */
756 RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */
757 RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */
758 RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */
759 RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */
760 RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */
761 RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */
762 RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */
763 RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */
764 RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */
765 RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */
766 RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */
767 RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */
768 RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */
769 RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */
770 RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */
771 RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */
772 RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */
773 RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */
774 RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */
775 RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */
776 RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */
777 RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */
778 RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */
779 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
780 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
781 RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */
782 RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */
783 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
784 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
785 RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */
786 RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */
787 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
788 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
789 RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */
790 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */
791 RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */
792 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */
793 RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */
794 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */
895 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
896 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
897 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
898 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
899 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
900 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
901 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
905 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
906 …RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on em…
910 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
911 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
912 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
913 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
914 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
915 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
916 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
917 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
918 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
919 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
920 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
921 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
922 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
923 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
924 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
925 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
926 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
927 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
931 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
932 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
936 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
937 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
938 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
939 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x314, BIT(16 + 4)), /* i2c3_sdam0 */
940 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x314, BIT(16 + 4) | BIT(4)), /* i2c3_sdam1 */
941 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
942 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
943 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
944 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
945 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
946 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
947 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
948 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
952 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
953 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
954 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
955 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
956 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
957 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
958 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
959 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
960 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
961 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
962 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
963 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
967 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
968 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
969 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
970 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
971 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
975 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
976 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
977 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
978 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
979 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
980 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
981 RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
982 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
983 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
984 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
985 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
986 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
987 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
988 RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
989 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
990 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
991 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
992 RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
993 RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
994 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
995 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
996 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
997 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
998 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
999 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
1000 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
1001 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
1002 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
1003 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
1004 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
1005 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
1006 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
1007 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
1008 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
1009 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
1010 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
1011 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
1012 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
1013 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
1014 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
1015 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
1016 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
1017 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
1018 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
1019 RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
1020 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
1021 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
1022 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
1023 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
1024 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
1025 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
1026 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
1027 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
1028 RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
1029 RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
1030 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
1031 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
1032 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
1033 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
1034 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
1035 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
1036 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
1037 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
1038 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
1039 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
1040 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
1041 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
1042 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
1043 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
1044 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
1045 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
1046 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
1047 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
1048 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
1049 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
1050 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
1051 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
1052 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
1053 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
1054 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1055 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1056 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1057 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1058 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
1059 RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
1060 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
1061 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
1062 RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
1063 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
1064 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
1065 RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
1066 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
1067 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
1071 int mux, u32 *loc, u32 *reg, u32 *value) in rockchip_get_mux_route() argument
1073 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
1074 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_mux_route()
1078 for (i = 0; i < ctrl->niomux_routes; i++) { in rockchip_get_mux_route()
1079 data = &ctrl->iomux_routes[i]; in rockchip_get_mux_route()
1080 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
1081 (data->pin == pin) && (data->func == mux)) in rockchip_get_mux_route()
1085 if (i >= ctrl->niomux_routes) in rockchip_get_mux_route()
1088 *loc = data->route_location; in rockchip_get_mux_route()
1089 *reg = data->route_offset; in rockchip_get_mux_route()
1090 *value = data->route_val; in rockchip_get_mux_route()
1097 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux()
1098 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_mux()
1103 u8 bit; in rockchip_get_mux() local
1106 return -EINVAL; in rockchip_get_mux()
1108 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_get_mux()
1109 dev_err(info->dev, "pin %d is unrouted\n", pin); in rockchip_get_mux()
1110 return -EINVAL; in rockchip_get_mux()
1113 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_get_mux()
1116 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_get_mux()
1117 regmap = info->regmap_pmu; in rockchip_get_mux()
1118 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) in rockchip_get_mux()
1119 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base; in rockchip_get_mux()
1121 regmap = info->regmap_base; in rockchip_get_mux()
1123 /* get basic quadrupel of mux registers and the correct reg inside */ in rockchip_get_mux()
1124 mux_type = bank->iomux[iomux_num].type; in rockchip_get_mux()
1125 reg = bank->iomux[iomux_num].offset; in rockchip_get_mux()
1129 bit = (pin % 4) * 4; in rockchip_get_mux()
1134 bit = (pin % 8 % 5) * 3; in rockchip_get_mux()
1137 bit = (pin % 8) * 2; in rockchip_get_mux()
1141 if (bank->recalced_mask & BIT(pin)) in rockchip_get_mux()
1142 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); in rockchip_get_mux()
1144 if (ctrl->type == RK3576) { in rockchip_get_mux()
1145 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7)) in rockchip_get_mux()
1149 if (ctrl->type == RK3588) { in rockchip_get_mux()
1150 if (bank->bank_num == 0) { in rockchip_get_mux()
1154 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ in rockchip_get_mux()
1159 if (!(val & BIT(8))) in rockchip_get_mux()
1160 return ((val >> bit) & mask); in rockchip_get_mux()
1163 regmap = info->regmap_base; in rockchip_get_mux()
1165 } else if (bank->bank_num > 0) { in rockchip_get_mux()
1174 return ((val >> bit) & mask); in rockchip_get_mux()
1178 int pin, int mux) in rockchip_verify_mux() argument
1180 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_verify_mux()
1181 struct device *dev = info->dev; in rockchip_verify_mux()
1185 return -EINVAL; in rockchip_verify_mux()
1187 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_verify_mux()
1189 return -EINVAL; in rockchip_verify_mux()
1192 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { in rockchip_verify_mux()
1193 if (mux != RK_FUNC_GPIO) { in rockchip_verify_mux()
1194 dev_err(dev, "pin %d only supports a gpio mux\n", pin); in rockchip_verify_mux()
1195 return -ENOTSUPP; in rockchip_verify_mux()
1203 * Set a new mux function for a pin.
1205 * The register is divided into the upper and lower 16 bit. When changing
1207 * it seems the changed bits are marked in the upper 16 bit, while the
1208 * changed value gets set in the same offset in the lower 16 bit.
1209 * All pin settings seem to be 2 bit wide in both the upper and lower
1213 * @mux: new mux function to set
1215 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rockchip_set_mux() argument
1217 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_mux()
1218 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_mux()
1219 struct device *dev = info->dev; in rockchip_set_mux()
1223 u8 bit; in rockchip_set_mux() local
1226 ret = rockchip_verify_mux(bank, pin, mux); in rockchip_set_mux()
1230 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_set_mux()
1233 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); in rockchip_set_mux()
1235 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_set_mux()
1236 regmap = info->regmap_pmu; in rockchip_set_mux()
1237 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) in rockchip_set_mux()
1238 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base; in rockchip_set_mux()
1240 regmap = info->regmap_base; in rockchip_set_mux()
1242 /* get basic quadrupel of mux registers and the correct reg inside */ in rockchip_set_mux()
1243 mux_type = bank->iomux[iomux_num].type; in rockchip_set_mux()
1244 reg = bank->iomux[iomux_num].offset; in rockchip_set_mux()
1248 bit = (pin % 4) * 4; in rockchip_set_mux()
1253 bit = (pin % 8 % 5) * 3; in rockchip_set_mux()
1256 bit = (pin % 8) * 2; in rockchip_set_mux()
1260 if (bank->recalced_mask & BIT(pin)) in rockchip_set_mux()
1261 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); in rockchip_set_mux()
1263 if (ctrl->type == RK3576) { in rockchip_set_mux()
1264 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7)) in rockchip_set_mux()
1268 if (ctrl->type == RK3588) { in rockchip_set_mux()
1269 if (bank->bank_num == 0) { in rockchip_set_mux()
1271 if (mux < 8) { in rockchip_set_mux()
1272 reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */ in rockchip_set_mux()
1273 data = (mask << (bit + 16)); in rockchip_set_mux()
1275 data |= (mux & mask) << bit; in rockchip_set_mux()
1280 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ in rockchip_set_mux()
1281 data = (mask << (bit + 16)); in rockchip_set_mux()
1283 data |= 8 << bit; in rockchip_set_mux()
1287 data = (mask << (bit + 16)); in rockchip_set_mux()
1289 data |= mux << bit; in rockchip_set_mux()
1290 regmap = info->regmap_base; in rockchip_set_mux()
1294 data = (mask << (bit + 16)); in rockchip_set_mux()
1296 data |= (mux & mask) << bit; in rockchip_set_mux()
1300 } else if (bank->bank_num > 0) { in rockchip_set_mux()
1305 if (mux > mask) in rockchip_set_mux()
1306 return -EINVAL; in rockchip_set_mux()
1308 if (bank->route_mask & BIT(pin)) { in rockchip_set_mux()
1309 if (rockchip_get_mux_route(bank, pin, mux, &route_location, in rockchip_set_mux()
1316 route_regmap = info->regmap_pmu; in rockchip_set_mux()
1319 route_regmap = info->regmap_base; in rockchip_set_mux()
1329 data = (mask << (bit + 16)); in rockchip_set_mux()
1331 data |= (mux & mask) << bit; in rockchip_set_mux()
1345 int *reg, u8 *bit) in px30_calc_pull_reg_and_bit() argument
1347 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_pull_reg_and_bit()
1350 if (bank->bank_num == 0) { in px30_calc_pull_reg_and_bit()
1351 *regmap = info->regmap_pmu; in px30_calc_pull_reg_and_bit()
1354 *regmap = info->regmap_base; in px30_calc_pull_reg_and_bit()
1358 *reg -= 0x10; in px30_calc_pull_reg_and_bit()
1359 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; in px30_calc_pull_reg_and_bit()
1363 *bit = (pin_num % PX30_PULL_PINS_PER_REG); in px30_calc_pull_reg_and_bit()
1364 *bit *= PX30_PULL_BITS_PER_PIN; in px30_calc_pull_reg_and_bit()
1377 int *reg, u8 *bit) in px30_calc_drv_reg_and_bit() argument
1379 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_drv_reg_and_bit()
1382 if (bank->bank_num == 0) { in px30_calc_drv_reg_and_bit()
1383 *regmap = info->regmap_pmu; in px30_calc_drv_reg_and_bit()
1386 *regmap = info->regmap_base; in px30_calc_drv_reg_and_bit()
1390 *reg -= 0x10; in px30_calc_drv_reg_and_bit()
1391 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; in px30_calc_drv_reg_and_bit()
1395 *bit = (pin_num % PX30_DRV_PINS_PER_REG); in px30_calc_drv_reg_and_bit()
1396 *bit *= PX30_DRV_BITS_PER_PIN; in px30_calc_drv_reg_and_bit()
1410 int *reg, u8 *bit) in px30_calc_schmitt_reg_and_bit() argument
1412 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_schmitt_reg_and_bit()
1415 if (bank->bank_num == 0) { in px30_calc_schmitt_reg_and_bit()
1416 *regmap = info->regmap_pmu; in px30_calc_schmitt_reg_and_bit()
1420 *regmap = info->regmap_base; in px30_calc_schmitt_reg_and_bit()
1423 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; in px30_calc_schmitt_reg_and_bit()
1427 *bit = pin_num % pins_per_reg; in px30_calc_schmitt_reg_and_bit()
1440 int *reg, u8 *bit) in rv1108_calc_pull_reg_and_bit() argument
1442 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_pull_reg_and_bit()
1445 if (bank->bank_num == 0) { in rv1108_calc_pull_reg_and_bit()
1446 *regmap = info->regmap_pmu; in rv1108_calc_pull_reg_and_bit()
1450 *regmap = info->regmap_base; in rv1108_calc_pull_reg_and_bit()
1452 *reg -= 0x10; in rv1108_calc_pull_reg_and_bit()
1453 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; in rv1108_calc_pull_reg_and_bit()
1457 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); in rv1108_calc_pull_reg_and_bit()
1458 *bit *= RV1108_PULL_BITS_PER_PIN; in rv1108_calc_pull_reg_and_bit()
1471 int *reg, u8 *bit) in rv1108_calc_drv_reg_and_bit() argument
1473 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_drv_reg_and_bit()
1476 if (bank->bank_num == 0) { in rv1108_calc_drv_reg_and_bit()
1477 *regmap = info->regmap_pmu; in rv1108_calc_drv_reg_and_bit()
1480 *regmap = info->regmap_base; in rv1108_calc_drv_reg_and_bit()
1484 *reg -= 0x10; in rv1108_calc_drv_reg_and_bit()
1485 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; in rv1108_calc_drv_reg_and_bit()
1489 *bit = pin_num % RV1108_DRV_PINS_PER_REG; in rv1108_calc_drv_reg_and_bit()
1490 *bit *= RV1108_DRV_BITS_PER_PIN; in rv1108_calc_drv_reg_and_bit()
1504 int *reg, u8 *bit) in rv1108_calc_schmitt_reg_and_bit() argument
1506 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_schmitt_reg_and_bit()
1509 if (bank->bank_num == 0) { in rv1108_calc_schmitt_reg_and_bit()
1510 *regmap = info->regmap_pmu; in rv1108_calc_schmitt_reg_and_bit()
1514 *regmap = info->regmap_base; in rv1108_calc_schmitt_reg_and_bit()
1517 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; in rv1108_calc_schmitt_reg_and_bit()
1520 *bit = pin_num % pins_per_reg; in rv1108_calc_schmitt_reg_and_bit()
1534 int *reg, u8 *bit) in rv1126_calc_pull_reg_and_bit() argument
1536 struct rockchip_pinctrl *info = bank->drvdata; in rv1126_calc_pull_reg_and_bit()
1539 if (bank->bank_num == 0) { in rv1126_calc_pull_reg_and_bit()
1541 *regmap = info->regmap_base; in rv1126_calc_pull_reg_and_bit()
1543 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); in rv1126_calc_pull_reg_and_bit()
1544 *bit = pin_num % RV1126_PULL_PINS_PER_REG; in rv1126_calc_pull_reg_and_bit()
1545 *bit *= RV1126_PULL_BITS_PER_PIN; in rv1126_calc_pull_reg_and_bit()
1548 *regmap = info->regmap_pmu; in rv1126_calc_pull_reg_and_bit()
1552 *regmap = info->regmap_base; in rv1126_calc_pull_reg_and_bit()
1553 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE; in rv1126_calc_pull_reg_and_bit()
1557 *bit = (pin_num % RV1126_PULL_PINS_PER_REG); in rv1126_calc_pull_reg_and_bit()
1558 *bit *= RV1126_PULL_BITS_PER_PIN; in rv1126_calc_pull_reg_and_bit()
1571 int *reg, u8 *bit) in rv1126_calc_drv_reg_and_bit() argument
1573 struct rockchip_pinctrl *info = bank->drvdata; in rv1126_calc_drv_reg_and_bit()
1576 if (bank->bank_num == 0) { in rv1126_calc_drv_reg_and_bit()
1578 *regmap = info->regmap_base; in rv1126_calc_drv_reg_and_bit()
1580 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); in rv1126_calc_drv_reg_and_bit()
1581 *reg -= 0x4; in rv1126_calc_drv_reg_and_bit()
1582 *bit = pin_num % RV1126_DRV_PINS_PER_REG; in rv1126_calc_drv_reg_and_bit()
1583 *bit *= RV1126_DRV_BITS_PER_PIN; in rv1126_calc_drv_reg_and_bit()
1586 *regmap = info->regmap_pmu; in rv1126_calc_drv_reg_and_bit()
1589 *regmap = info->regmap_base; in rv1126_calc_drv_reg_and_bit()
1591 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE; in rv1126_calc_drv_reg_and_bit()
1595 *bit = pin_num % RV1126_DRV_PINS_PER_REG; in rv1126_calc_drv_reg_and_bit()
1596 *bit *= RV1126_DRV_BITS_PER_PIN; in rv1126_calc_drv_reg_and_bit()
1610 int *reg, u8 *bit) in rv1126_calc_schmitt_reg_and_bit() argument
1612 struct rockchip_pinctrl *info = bank->drvdata; in rv1126_calc_schmitt_reg_and_bit()
1615 if (bank->bank_num == 0) { in rv1126_calc_schmitt_reg_and_bit()
1617 *regmap = info->regmap_base; in rv1126_calc_schmitt_reg_and_bit()
1619 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); in rv1126_calc_schmitt_reg_and_bit()
1620 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG; in rv1126_calc_schmitt_reg_and_bit()
1623 *regmap = info->regmap_pmu; in rv1126_calc_schmitt_reg_and_bit()
1627 *regmap = info->regmap_base; in rv1126_calc_schmitt_reg_and_bit()
1630 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE; in rv1126_calc_schmitt_reg_and_bit()
1633 *bit = pin_num % pins_per_reg; in rv1126_calc_schmitt_reg_and_bit()
1644 int *reg, u8 *bit) in rk3308_calc_schmitt_reg_and_bit() argument
1646 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_schmitt_reg_and_bit()
1648 *regmap = info->regmap_base; in rk3308_calc_schmitt_reg_and_bit()
1651 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; in rk3308_calc_schmitt_reg_and_bit()
1653 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; in rk3308_calc_schmitt_reg_and_bit()
1664 int *reg, u8 *bit) in rk2928_calc_pull_reg_and_bit() argument
1666 struct rockchip_pinctrl *info = bank->drvdata; in rk2928_calc_pull_reg_and_bit()
1668 *regmap = info->regmap_base; in rk2928_calc_pull_reg_and_bit()
1670 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk2928_calc_pull_reg_and_bit()
1673 *bit = pin_num % RK2928_PULL_PINS_PER_REG; in rk2928_calc_pull_reg_and_bit()
1682 int *reg, u8 *bit) in rk3128_calc_pull_reg_and_bit() argument
1684 struct rockchip_pinctrl *info = bank->drvdata; in rk3128_calc_pull_reg_and_bit()
1686 *regmap = info->regmap_base; in rk3128_calc_pull_reg_and_bit()
1688 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk3128_calc_pull_reg_and_bit()
1691 *bit = pin_num % RK2928_PULL_PINS_PER_REG; in rk3128_calc_pull_reg_and_bit()
1704 int *reg, u8 *bit) in rk3188_calc_pull_reg_and_bit() argument
1706 struct rockchip_pinctrl *info = bank->drvdata; in rk3188_calc_pull_reg_and_bit()
1709 if (bank->bank_num == 0 && pin_num < 12) { in rk3188_calc_pull_reg_and_bit()
1710 *regmap = info->regmap_pmu ? info->regmap_pmu in rk3188_calc_pull_reg_and_bit()
1711 : bank->regmap_pull; in rk3188_calc_pull_reg_and_bit()
1712 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; in rk3188_calc_pull_reg_and_bit()
1714 *bit = pin_num % RK3188_PULL_PINS_PER_REG; in rk3188_calc_pull_reg_and_bit()
1715 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3188_calc_pull_reg_and_bit()
1717 *regmap = info->regmap_pull ? info->regmap_pull in rk3188_calc_pull_reg_and_bit()
1718 : info->regmap_base; in rk3188_calc_pull_reg_and_bit()
1719 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; in rk3188_calc_pull_reg_and_bit()
1722 *reg -= 4; in rk3188_calc_pull_reg_and_bit()
1723 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3188_calc_pull_reg_and_bit()
1731 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); in rk3188_calc_pull_reg_and_bit()
1732 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3188_calc_pull_reg_and_bit()
1741 int *reg, u8 *bit) in rk3288_calc_pull_reg_and_bit() argument
1743 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_pull_reg_and_bit()
1746 if (bank->bank_num == 0) { in rk3288_calc_pull_reg_and_bit()
1747 *regmap = info->regmap_pmu; in rk3288_calc_pull_reg_and_bit()
1751 *bit = pin_num % RK3188_PULL_PINS_PER_REG; in rk3288_calc_pull_reg_and_bit()
1752 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3288_calc_pull_reg_and_bit()
1754 *regmap = info->regmap_base; in rk3288_calc_pull_reg_and_bit()
1758 *reg -= 0x10; in rk3288_calc_pull_reg_and_bit()
1759 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3288_calc_pull_reg_and_bit()
1762 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); in rk3288_calc_pull_reg_and_bit()
1763 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3288_calc_pull_reg_and_bit()
1777 int *reg, u8 *bit) in rk3288_calc_drv_reg_and_bit() argument
1779 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_drv_reg_and_bit()
1782 if (bank->bank_num == 0) { in rk3288_calc_drv_reg_and_bit()
1783 *regmap = info->regmap_pmu; in rk3288_calc_drv_reg_and_bit()
1787 *bit = pin_num % RK3288_DRV_PINS_PER_REG; in rk3288_calc_drv_reg_and_bit()
1788 *bit *= RK3288_DRV_BITS_PER_PIN; in rk3288_calc_drv_reg_and_bit()
1790 *regmap = info->regmap_base; in rk3288_calc_drv_reg_and_bit()
1794 *reg -= 0x10; in rk3288_calc_drv_reg_and_bit()
1795 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3288_calc_drv_reg_and_bit()
1798 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); in rk3288_calc_drv_reg_and_bit()
1799 *bit *= RK3288_DRV_BITS_PER_PIN; in rk3288_calc_drv_reg_and_bit()
1809 int *reg, u8 *bit) in rk3228_calc_pull_reg_and_bit() argument
1811 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_pull_reg_and_bit()
1813 *regmap = info->regmap_base; in rk3228_calc_pull_reg_and_bit()
1815 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3228_calc_pull_reg_and_bit()
1818 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); in rk3228_calc_pull_reg_and_bit()
1819 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3228_calc_pull_reg_and_bit()
1828 int *reg, u8 *bit) in rk3228_calc_drv_reg_and_bit() argument
1830 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_drv_reg_and_bit()
1832 *regmap = info->regmap_base; in rk3228_calc_drv_reg_and_bit()
1834 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3228_calc_drv_reg_and_bit()
1837 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); in rk3228_calc_drv_reg_and_bit()
1838 *bit *= RK3288_DRV_BITS_PER_PIN; in rk3228_calc_drv_reg_and_bit()
1847 int *reg, u8 *bit) in rk3308_calc_pull_reg_and_bit() argument
1849 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_pull_reg_and_bit()
1851 *regmap = info->regmap_base; in rk3308_calc_pull_reg_and_bit()
1853 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3308_calc_pull_reg_and_bit()
1856 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); in rk3308_calc_pull_reg_and_bit()
1857 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3308_calc_pull_reg_and_bit()
1866 int *reg, u8 *bit) in rk3308_calc_drv_reg_and_bit() argument
1868 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_drv_reg_and_bit()
1870 *regmap = info->regmap_base; in rk3308_calc_drv_reg_and_bit()
1872 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3308_calc_drv_reg_and_bit()
1875 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); in rk3308_calc_drv_reg_and_bit()
1876 *bit *= RK3288_DRV_BITS_PER_PIN; in rk3308_calc_drv_reg_and_bit()
1886 int *reg, u8 *bit) in rk3368_calc_pull_reg_and_bit() argument
1888 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_pull_reg_and_bit()
1891 if (bank->bank_num == 0) { in rk3368_calc_pull_reg_and_bit()
1892 *regmap = info->regmap_pmu; in rk3368_calc_pull_reg_and_bit()
1896 *bit = pin_num % RK3188_PULL_PINS_PER_REG; in rk3368_calc_pull_reg_and_bit()
1897 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3368_calc_pull_reg_and_bit()
1899 *regmap = info->regmap_base; in rk3368_calc_pull_reg_and_bit()
1903 *reg -= 0x10; in rk3368_calc_pull_reg_and_bit()
1904 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3368_calc_pull_reg_and_bit()
1907 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); in rk3368_calc_pull_reg_and_bit()
1908 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3368_calc_pull_reg_and_bit()
1919 int *reg, u8 *bit) in rk3368_calc_drv_reg_and_bit() argument
1921 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_drv_reg_and_bit()
1924 if (bank->bank_num == 0) { in rk3368_calc_drv_reg_and_bit()
1925 *regmap = info->regmap_pmu; in rk3368_calc_drv_reg_and_bit()
1929 *bit = pin_num % RK3288_DRV_PINS_PER_REG; in rk3368_calc_drv_reg_and_bit()
1930 *bit *= RK3288_DRV_BITS_PER_PIN; in rk3368_calc_drv_reg_and_bit()
1932 *regmap = info->regmap_base; in rk3368_calc_drv_reg_and_bit()
1936 *reg -= 0x10; in rk3368_calc_drv_reg_and_bit()
1937 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3368_calc_drv_reg_and_bit()
1940 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); in rk3368_calc_drv_reg_and_bit()
1941 *bit *= RK3288_DRV_BITS_PER_PIN; in rk3368_calc_drv_reg_and_bit()
1953 int *reg, u8 *bit) in rk3399_calc_pull_reg_and_bit() argument
1955 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_pull_reg_and_bit()
1958 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { in rk3399_calc_pull_reg_and_bit()
1959 *regmap = info->regmap_pmu; in rk3399_calc_pull_reg_and_bit()
1962 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
1965 *bit = pin_num % RK3188_PULL_PINS_PER_REG; in rk3399_calc_pull_reg_and_bit()
1966 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3399_calc_pull_reg_and_bit()
1968 *regmap = info->regmap_base; in rk3399_calc_pull_reg_and_bit()
1972 *reg -= 0x20; in rk3399_calc_pull_reg_and_bit()
1973 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
1976 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); in rk3399_calc_pull_reg_and_bit()
1977 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3399_calc_pull_reg_and_bit()
1985 int *reg, u8 *bit) in rk3399_calc_drv_reg_and_bit() argument
1987 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_drv_reg_and_bit()
1991 if ((bank->bank_num == 0) || (bank->bank_num == 1)) in rk3399_calc_drv_reg_and_bit()
1992 *regmap = info->regmap_pmu; in rk3399_calc_drv_reg_and_bit()
1994 *regmap = info->regmap_base; in rk3399_calc_drv_reg_and_bit()
1996 *reg = bank->drv[drv_num].offset; in rk3399_calc_drv_reg_and_bit()
1997 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rk3399_calc_drv_reg_and_bit()
1998 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) in rk3399_calc_drv_reg_and_bit()
1999 *bit = (pin_num % 8) * 3; in rk3399_calc_drv_reg_and_bit()
2001 *bit = (pin_num % 8) * 2; in rk3399_calc_drv_reg_and_bit()
2014 int *reg, u8 *bit) in rk3568_calc_pull_reg_and_bit() argument
2016 struct rockchip_pinctrl *info = bank->drvdata; in rk3568_calc_pull_reg_and_bit()
2018 if (bank->bank_num == 0) { in rk3568_calc_pull_reg_and_bit()
2019 *regmap = info->regmap_pmu; in rk3568_calc_pull_reg_and_bit()
2021 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; in rk3568_calc_pull_reg_and_bit()
2024 *bit = pin_num % RK3568_PULL_PINS_PER_REG; in rk3568_calc_pull_reg_and_bit()
2025 *bit *= RK3568_PULL_BITS_PER_PIN; in rk3568_calc_pull_reg_and_bit()
2027 *regmap = info->regmap_base; in rk3568_calc_pull_reg_and_bit()
2029 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; in rk3568_calc_pull_reg_and_bit()
2032 *bit = (pin_num % RK3568_PULL_PINS_PER_REG); in rk3568_calc_pull_reg_and_bit()
2033 *bit *= RK3568_PULL_BITS_PER_PIN; in rk3568_calc_pull_reg_and_bit()
2047 int *reg, u8 *bit) in rk3568_calc_drv_reg_and_bit() argument
2049 struct rockchip_pinctrl *info = bank->drvdata; in rk3568_calc_drv_reg_and_bit()
2052 if (bank->bank_num == 0) { in rk3568_calc_drv_reg_and_bit()
2053 *regmap = info->regmap_pmu; in rk3568_calc_drv_reg_and_bit()
2057 *bit = pin_num % RK3568_DRV_PINS_PER_REG; in rk3568_calc_drv_reg_and_bit()
2058 *bit *= RK3568_DRV_BITS_PER_PIN; in rk3568_calc_drv_reg_and_bit()
2060 *regmap = info->regmap_base; in rk3568_calc_drv_reg_and_bit()
2062 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; in rk3568_calc_drv_reg_and_bit()
2065 *bit = (pin_num % RK3568_DRV_PINS_PER_REG); in rk3568_calc_drv_reg_and_bit()
2066 *bit *= RK3568_DRV_BITS_PER_PIN; in rk3568_calc_drv_reg_and_bit()
2085 int *reg, u8 *bit) in rk3576_calc_drv_reg_and_bit() argument
2087 struct rockchip_pinctrl *info = bank->drvdata; in rk3576_calc_drv_reg_and_bit()
2089 *regmap = info->regmap_base; in rk3576_calc_drv_reg_and_bit()
2091 if (bank->bank_num == 0 && pin_num < 12) in rk3576_calc_drv_reg_and_bit()
2093 else if (bank->bank_num == 0) in rk3576_calc_drv_reg_and_bit()
2094 *reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc; in rk3576_calc_drv_reg_and_bit()
2095 else if (bank->bank_num == 1) in rk3576_calc_drv_reg_and_bit()
2097 else if (bank->bank_num == 2) in rk3576_calc_drv_reg_and_bit()
2099 else if (bank->bank_num == 3) in rk3576_calc_drv_reg_and_bit()
2101 else if (bank->bank_num == 4 && pin_num < 16) in rk3576_calc_drv_reg_and_bit()
2103 else if (bank->bank_num == 4 && pin_num < 24) in rk3576_calc_drv_reg_and_bit()
2104 *reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10; in rk3576_calc_drv_reg_and_bit()
2105 else if (bank->bank_num == 4) in rk3576_calc_drv_reg_and_bit()
2106 *reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18; in rk3576_calc_drv_reg_and_bit()
2108 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); in rk3576_calc_drv_reg_and_bit()
2111 *bit = pin_num % RK3576_DRV_PINS_PER_REG; in rk3576_calc_drv_reg_and_bit()
2112 *bit *= RK3576_DRV_BITS_PER_PIN; in rk3576_calc_drv_reg_and_bit()
2130 int *reg, u8 *bit) in rk3576_calc_pull_reg_and_bit() argument
2132 struct rockchip_pinctrl *info = bank->drvdata; in rk3576_calc_pull_reg_and_bit()
2134 *regmap = info->regmap_base; in rk3576_calc_pull_reg_and_bit()
2136 if (bank->bank_num == 0 && pin_num < 12) in rk3576_calc_pull_reg_and_bit()
2138 else if (bank->bank_num == 0) in rk3576_calc_pull_reg_and_bit()
2139 *reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4; in rk3576_calc_pull_reg_and_bit()
2140 else if (bank->bank_num == 1) in rk3576_calc_pull_reg_and_bit()
2142 else if (bank->bank_num == 2) in rk3576_calc_pull_reg_and_bit()
2144 else if (bank->bank_num == 3) in rk3576_calc_pull_reg_and_bit()
2146 else if (bank->bank_num == 4 && pin_num < 16) in rk3576_calc_pull_reg_and_bit()
2148 else if (bank->bank_num == 4 && pin_num < 24) in rk3576_calc_pull_reg_and_bit()
2149 *reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8; in rk3576_calc_pull_reg_and_bit()
2150 else if (bank->bank_num == 4) in rk3576_calc_pull_reg_and_bit()
2151 *reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc; in rk3576_calc_pull_reg_and_bit()
2153 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); in rk3576_calc_pull_reg_and_bit()
2156 *bit = pin_num % RK3576_PULL_PINS_PER_REG; in rk3576_calc_pull_reg_and_bit()
2157 *bit *= RK3576_PULL_BITS_PER_PIN; in rk3576_calc_pull_reg_and_bit()
2176 int *reg, u8 *bit) in rk3576_calc_schmitt_reg_and_bit() argument
2178 struct rockchip_pinctrl *info = bank->drvdata; in rk3576_calc_schmitt_reg_and_bit()
2180 *regmap = info->regmap_base; in rk3576_calc_schmitt_reg_and_bit()
2182 if (bank->bank_num == 0 && pin_num < 12) in rk3576_calc_schmitt_reg_and_bit()
2184 else if (bank->bank_num == 0) in rk3576_calc_schmitt_reg_and_bit()
2185 *reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4; in rk3576_calc_schmitt_reg_and_bit()
2186 else if (bank->bank_num == 1) in rk3576_calc_schmitt_reg_and_bit()
2188 else if (bank->bank_num == 2) in rk3576_calc_schmitt_reg_and_bit()
2190 else if (bank->bank_num == 3) in rk3576_calc_schmitt_reg_and_bit()
2192 else if (bank->bank_num == 4 && pin_num < 16) in rk3576_calc_schmitt_reg_and_bit()
2194 else if (bank->bank_num == 4 && pin_num < 24) in rk3576_calc_schmitt_reg_and_bit()
2195 *reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8; in rk3576_calc_schmitt_reg_and_bit()
2196 else if (bank->bank_num == 4) in rk3576_calc_schmitt_reg_and_bit()
2197 *reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc; in rk3576_calc_schmitt_reg_and_bit()
2199 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); in rk3576_calc_schmitt_reg_and_bit()
2202 *bit = pin_num % RK3576_SMT_PINS_PER_REG; in rk3576_calc_schmitt_reg_and_bit()
2203 *bit *= RK3576_SMT_BITS_PER_PIN; in rk3576_calc_schmitt_reg_and_bit()
2318 int *reg, u8 *bit) in rk3588_calc_pull_reg_and_bit() argument
2320 struct rockchip_pinctrl *info = bank->drvdata; in rk3588_calc_pull_reg_and_bit()
2321 u8 bank_num = bank->bank_num; in rk3588_calc_pull_reg_and_bit()
2325 for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) { in rk3588_calc_pull_reg_and_bit()
2328 *regmap = info->regmap_base; in rk3588_calc_pull_reg_and_bit()
2329 *bit = pin_num % RK3588_PULL_PINS_PER_REG; in rk3588_calc_pull_reg_and_bit()
2330 *bit *= RK3588_PULL_BITS_PER_PIN; in rk3588_calc_pull_reg_and_bit()
2335 return -EINVAL; in rk3588_calc_pull_reg_and_bit()
2343 int *reg, u8 *bit) in rk3588_calc_drv_reg_and_bit() argument
2345 struct rockchip_pinctrl *info = bank->drvdata; in rk3588_calc_drv_reg_and_bit()
2346 u8 bank_num = bank->bank_num; in rk3588_calc_drv_reg_and_bit()
2350 for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) { in rk3588_calc_drv_reg_and_bit()
2353 *regmap = info->regmap_base; in rk3588_calc_drv_reg_and_bit()
2354 *bit = pin_num % RK3588_DRV_PINS_PER_REG; in rk3588_calc_drv_reg_and_bit()
2355 *bit *= RK3588_DRV_BITS_PER_PIN; in rk3588_calc_drv_reg_and_bit()
2360 return -EINVAL; in rk3588_calc_drv_reg_and_bit()
2369 int *reg, u8 *bit) in rk3588_calc_schmitt_reg_and_bit() argument
2371 struct rockchip_pinctrl *info = bank->drvdata; in rk3588_calc_schmitt_reg_and_bit()
2372 u8 bank_num = bank->bank_num; in rk3588_calc_schmitt_reg_and_bit()
2376 for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) { in rk3588_calc_schmitt_reg_and_bit()
2379 *regmap = info->regmap_base; in rk3588_calc_schmitt_reg_and_bit()
2380 *bit = pin_num % RK3588_SMT_PINS_PER_REG; in rk3588_calc_schmitt_reg_and_bit()
2381 *bit *= RK3588_SMT_BITS_PER_PIN; in rk3588_calc_schmitt_reg_and_bit()
2386 return -EINVAL; in rk3588_calc_schmitt_reg_and_bit()
2390 { 2, 4, 8, 12, -1, -1, -1, -1 },
2391 { 3, 6, 9, 12, -1, -1, -1, -1 },
2392 { 5, 10, 15, 20, -1, -1, -1, -1 },
2400 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_drive_perpin()
2401 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_drive_perpin()
2402 struct device *dev = info->dev; in rockchip_get_drive_perpin()
2406 u8 bit; in rockchip_get_drive_perpin() local
2407 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_get_drive_perpin()
2409 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_drive_perpin()
2417 switch (bit) { in rockchip_get_drive_perpin()
2423 * drive-strength offset is special, as it is in rockchip_get_drive_perpin()
2435 * the bit data[15] contains bit 0 of the value in rockchip_get_drive_perpin()
2447 bit -= 16; in rockchip_get_drive_perpin()
2450 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", in rockchip_get_drive_perpin()
2451 bit, drv_type); in rockchip_get_drive_perpin()
2452 return -EINVAL; in rockchip_get_drive_perpin()
2463 return -EINVAL; in rockchip_get_drive_perpin()
2470 data >>= bit; in rockchip_get_drive_perpin()
2471 data &= (1 << rmask_bits) - 1; in rockchip_get_drive_perpin()
2479 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_drive_perpin()
2480 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_drive_perpin()
2481 struct device *dev = info->dev; in rockchip_set_drive_perpin()
2485 u8 bit; in rockchip_set_drive_perpin() local
2486 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_set_drive_perpin()
2488 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n", in rockchip_set_drive_perpin()
2489 bank->bank_num, pin_num, strength); in rockchip_set_drive_perpin()
2491 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_drive_perpin()
2494 if (ctrl->type == RK3588) { in rockchip_set_drive_perpin()
2498 } else if (ctrl->type == RK3568) { in rockchip_set_drive_perpin()
2500 ret = (1 << (strength + 1)) - 1; in rockchip_set_drive_perpin()
2502 } else if (ctrl->type == RK3576) { in rockchip_set_drive_perpin()
2504 ret = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1)); in rockchip_set_drive_perpin()
2508 if (ctrl->type == RV1126) { in rockchip_set_drive_perpin()
2514 ret = -EINVAL; in rockchip_set_drive_perpin()
2534 switch (bit) { in rockchip_set_drive_perpin()
2540 * drive-strength offset is special, as it is spread in rockchip_set_drive_perpin()
2541 * over 2 registers, the bit data[15] contains bit 0 in rockchip_set_drive_perpin()
2547 rmask = BIT(15) | BIT(31); in rockchip_set_drive_perpin()
2548 data |= BIT(31); in rockchip_set_drive_perpin()
2562 bit -= 16; in rockchip_set_drive_perpin()
2565 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", in rockchip_set_drive_perpin()
2566 bit, drv_type); in rockchip_set_drive_perpin()
2567 return -EINVAL; in rockchip_set_drive_perpin()
2577 return -EINVAL; in rockchip_set_drive_perpin()
2582 data = ((1 << rmask_bits) - 1) << (bit + 16); in rockchip_set_drive_perpin()
2584 data |= (ret << bit); in rockchip_set_drive_perpin()
2608 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_pull()
2609 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_pull()
2610 struct device *dev = info->dev; in rockchip_get_pull()
2613 u8 bit; in rockchip_get_pull() local
2617 if (ctrl->type == RK3066B) in rockchip_get_pull()
2620 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_pull()
2628 switch (ctrl->type) { in rockchip_get_pull()
2631 return !(data & BIT(bit)) in rockchip_get_pull()
2645 pull_type = bank->pull_type[pin_num / 8]; in rockchip_get_pull()
2646 data >>= bit; in rockchip_get_pull()
2647 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; in rockchip_get_pull()
2649 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, in rockchip_get_pull()
2652 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { in rockchip_get_pull()
2660 return -EINVAL; in rockchip_get_pull()
2667 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_pull()
2668 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_pull()
2669 struct device *dev = info->dev; in rockchip_set_pull()
2672 u8 bit; in rockchip_set_pull() local
2675 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull); in rockchip_set_pull()
2678 if (ctrl->type == RK3066B) in rockchip_set_pull()
2679 return pull ? -EINVAL : 0; in rockchip_set_pull()
2681 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_pull()
2685 switch (ctrl->type) { in rockchip_set_pull()
2688 data = BIT(bit + 16); in rockchip_set_pull()
2690 data |= BIT(bit); in rockchip_set_pull()
2705 pull_type = bank->pull_type[pin_num / 8]; in rockchip_set_pull()
2706 ret = -EINVAL; in rockchip_set_pull()
2715 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, in rockchip_set_pull()
2718 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { in rockchip_set_pull()
2729 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); in rockchip_set_pull()
2731 data |= (ret << bit); in rockchip_set_pull()
2737 return -EINVAL; in rockchip_set_pull()
2751 int *reg, u8 *bit) in rk3328_calc_schmitt_reg_and_bit() argument
2753 struct rockchip_pinctrl *info = bank->drvdata; in rk3328_calc_schmitt_reg_and_bit()
2755 *regmap = info->regmap_base; in rk3328_calc_schmitt_reg_and_bit()
2758 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; in rk3328_calc_schmitt_reg_and_bit()
2760 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; in rk3328_calc_schmitt_reg_and_bit()
2774 int *reg, u8 *bit) in rk3568_calc_schmitt_reg_and_bit() argument
2776 struct rockchip_pinctrl *info = bank->drvdata; in rk3568_calc_schmitt_reg_and_bit()
2778 if (bank->bank_num == 0) { in rk3568_calc_schmitt_reg_and_bit()
2779 *regmap = info->regmap_pmu; in rk3568_calc_schmitt_reg_and_bit()
2782 *regmap = info->regmap_base; in rk3568_calc_schmitt_reg_and_bit()
2784 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; in rk3568_calc_schmitt_reg_and_bit()
2788 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG; in rk3568_calc_schmitt_reg_and_bit()
2789 *bit *= RK3568_SCHMITT_BITS_PER_PIN; in rk3568_calc_schmitt_reg_and_bit()
2796 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_schmitt()
2797 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_schmitt()
2800 u8 bit; in rockchip_get_schmitt() local
2803 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_schmitt()
2811 data >>= bit; in rockchip_get_schmitt()
2812 switch (ctrl->type) { in rockchip_get_schmitt()
2814 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1); in rockchip_get_schmitt()
2825 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_schmitt()
2826 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_schmitt()
2827 struct device *dev = info->dev; in rockchip_set_schmitt()
2830 u8 bit; in rockchip_set_schmitt() local
2833 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n", in rockchip_set_schmitt()
2834 bank->bank_num, pin_num, enable); in rockchip_set_schmitt()
2836 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_schmitt()
2841 switch (ctrl->type) { in rockchip_set_schmitt()
2843 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); in rockchip_set_schmitt()
2845 data |= ((enable ? 0x2 : 0x1) << bit); in rockchip_set_schmitt()
2848 data = BIT(bit + 16) | (enable << bit); in rockchip_set_schmitt()
2849 rmask = BIT(bit + 16) | BIT(bit); in rockchip_set_schmitt()
2864 return info->nfunctions; in rockchip_pmx_get_funcs_count()
2872 return info->functions[selector].name; in rockchip_pmx_get_func_name()
2881 *groups = info->functions[selector].groups; in rockchip_pmx_get_groups()
2882 *num_groups = info->functions[selector].ngroups; in rockchip_pmx_get_groups()
2891 const unsigned int *pins = info->groups[group].pins; in rockchip_pmx_set()
2892 const struct rockchip_pin_config *data = info->groups[group].data; in rockchip_pmx_set()
2893 struct device *dev = info->dev; in rockchip_pmx_set()
2898 info->functions[selector].name, info->groups[group].name); in rockchip_pmx_set()
2904 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { in rockchip_pmx_set()
2906 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, in rockchip_pmx_set()
2914 for (cnt--; cnt >= 0; cnt--) { in rockchip_pmx_set()
2916 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); in rockchip_pmx_set()
2934 return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO); in rockchip_pmx_gpio_set_direction()
2952 switch (ctrl->type) { in rockchip_pinconf_pull_valid()
2984 return -ENOMEM; in rockchip_pinconf_defer_pin()
2986 cfg->pin = pin; in rockchip_pinconf_defer_pin()
2987 cfg->param = param; in rockchip_pinconf_defer_pin()
2988 cfg->arg = arg; in rockchip_pinconf_defer_pin()
2990 list_add_tail(&cfg->head, &bank->deferred_pins); in rockchip_pinconf_defer_pin()
3001 struct gpio_chip *gpio = &bank->gpio_chip; in rockchip_pinconf_set()
3014 * The lock makes sure that either gpio-probe has completed in rockchip_pinconf_set()
3017 mutex_lock(&bank->deferred_lock); in rockchip_pinconf_set()
3018 if (!gpio || !gpio->direction_output) { in rockchip_pinconf_set()
3019 rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param, in rockchip_pinconf_set()
3021 mutex_unlock(&bank->deferred_lock); in rockchip_pinconf_set()
3027 mutex_unlock(&bank->deferred_lock); in rockchip_pinconf_set()
3032 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
3041 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) in rockchip_pinconf_set()
3042 return -ENOTSUPP; in rockchip_pinconf_set()
3045 return -EINVAL; in rockchip_pinconf_set()
3047 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
3053 rc = rockchip_set_mux(bank, pin - bank->pin_base, in rockchip_pinconf_set()
3056 return -EINVAL; in rockchip_pinconf_set()
3058 rc = gpio->direction_output(gpio, pin - bank->pin_base, in rockchip_pinconf_set()
3064 rc = rockchip_set_mux(bank, pin - bank->pin_base, in rockchip_pinconf_set()
3067 return -EINVAL; in rockchip_pinconf_set()
3069 rc = gpio->direction_input(gpio, pin - bank->pin_base); in rockchip_pinconf_set()
3074 /* rk3288 is the first with per-pin drive-strength */ in rockchip_pinconf_set()
3075 if (!info->ctrl->drv_calc_reg) in rockchip_pinconf_set()
3076 return -ENOTSUPP; in rockchip_pinconf_set()
3079 pin - bank->pin_base, arg); in rockchip_pinconf_set()
3084 if (!info->ctrl->schmitt_calc_reg) in rockchip_pinconf_set()
3085 return -ENOTSUPP; in rockchip_pinconf_set()
3088 pin - bank->pin_base, arg); in rockchip_pinconf_set()
3093 return -ENOTSUPP; in rockchip_pinconf_set()
3107 struct gpio_chip *gpio = &bank->gpio_chip; in rockchip_pinconf_get()
3114 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
3115 return -EINVAL; in rockchip_pinconf_get()
3123 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) in rockchip_pinconf_get()
3124 return -ENOTSUPP; in rockchip_pinconf_get()
3126 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
3127 return -EINVAL; in rockchip_pinconf_get()
3132 rc = rockchip_get_mux(bank, pin - bank->pin_base); in rockchip_pinconf_get()
3134 return -EINVAL; in rockchip_pinconf_get()
3136 if (!gpio || !gpio->get) { in rockchip_pinconf_get()
3141 rc = gpio->get(gpio, pin - bank->pin_base); in rockchip_pinconf_get()
3148 /* rk3288 is the first with per-pin drive-strength */ in rockchip_pinconf_get()
3149 if (!info->ctrl->drv_calc_reg) in rockchip_pinconf_get()
3150 return -ENOTSUPP; in rockchip_pinconf_get()
3152 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); in rockchip_pinconf_get()
3159 if (!info->ctrl->schmitt_calc_reg) in rockchip_pinconf_get()
3160 return -ENOTSUPP; in rockchip_pinconf_get()
3162 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); in rockchip_pinconf_get()
3169 return -ENOTSUPP; in rockchip_pinconf_get()
3185 { .compatible = "rockchip,gpio-bank" },
3186 { .compatible = "rockchip,rk3188-gpio-bank0" },
3199 info->nfunctions++; in rockchip_pinctrl_child_count()
3200 info->ngroups += of_get_child_count(child); in rockchip_pinctrl_child_count()
3209 struct device *dev = info->dev; in rockchip_pinctrl_parse_groups()
3220 grp->name = np->name; in rockchip_pinctrl_parse_groups()
3223 * the binding format is rockchip,pins = <bank pin mux CONFIG>, in rockchip_pinctrl_parse_groups()
3230 return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n"); in rockchip_pinctrl_parse_groups()
3232 grp->npins = size / 4; in rockchip_pinctrl_parse_groups()
3234 grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL); in rockchip_pinctrl_parse_groups()
3235 grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL); in rockchip_pinctrl_parse_groups()
3236 if (!grp->pins || !grp->data) in rockchip_pinctrl_parse_groups()
3237 return -ENOMEM; in rockchip_pinctrl_parse_groups()
3248 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
3249 grp->data[j].func = be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
3253 return -EINVAL; in rockchip_pinctrl_parse_groups()
3257 &grp->data[j].configs, &grp->data[j].nconfigs); in rockchip_pinctrl_parse_groups()
3270 struct device *dev = info->dev; in rockchip_pinctrl_parse_functions()
3279 func = &info->functions[index]; in rockchip_pinctrl_parse_functions()
3282 func->name = np->name; in rockchip_pinctrl_parse_functions()
3283 func->ngroups = of_get_child_count(np); in rockchip_pinctrl_parse_functions()
3284 if (func->ngroups <= 0) in rockchip_pinctrl_parse_functions()
3287 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); in rockchip_pinctrl_parse_functions()
3288 if (!func->groups) in rockchip_pinctrl_parse_functions()
3289 return -ENOMEM; in rockchip_pinctrl_parse_functions()
3292 func->groups[i] = child->name; in rockchip_pinctrl_parse_functions()
3293 grp = &info->groups[grp_index++]; in rockchip_pinctrl_parse_functions()
3305 struct device *dev = &pdev->dev; in rockchip_pinctrl_parse_dt()
3306 struct device_node *np = dev->of_node; in rockchip_pinctrl_parse_dt()
3312 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); in rockchip_pinctrl_parse_dt()
3313 dev_dbg(dev, "ngroups = %d\n", info->ngroups); in rockchip_pinctrl_parse_dt()
3315 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); in rockchip_pinctrl_parse_dt()
3316 if (!info->functions) in rockchip_pinctrl_parse_dt()
3317 return -ENOMEM; in rockchip_pinctrl_parse_dt()
3319 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); in rockchip_pinctrl_parse_dt()
3320 if (!info->groups) in rockchip_pinctrl_parse_dt()
3321 return -ENOMEM; in rockchip_pinctrl_parse_dt()
3342 struct pinctrl_desc *ctrldesc = &info->pctl; in rockchip_pinctrl_register()
3345 struct device *dev = &pdev->dev; in rockchip_pinctrl_register()
3350 ctrldesc->name = "rockchip-pinctrl"; in rockchip_pinctrl_register()
3351 ctrldesc->owner = THIS_MODULE; in rockchip_pinctrl_register()
3352 ctrldesc->pctlops = &rockchip_pctrl_ops; in rockchip_pinctrl_register()
3353 ctrldesc->pmxops = &rockchip_pmx_ops; in rockchip_pinctrl_register()
3354 ctrldesc->confops = &rockchip_pinconf_ops; in rockchip_pinctrl_register()
3356 pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL); in rockchip_pinctrl_register()
3358 return -ENOMEM; in rockchip_pinctrl_register()
3360 ctrldesc->pins = pindesc; in rockchip_pinctrl_register()
3361 ctrldesc->npins = info->ctrl->nr_pins; in rockchip_pinctrl_register()
3364 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) { in rockchip_pinctrl_register()
3365 pin_bank = &info->ctrl->pin_banks[bank]; in rockchip_pinctrl_register()
3367 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins); in rockchip_pinctrl_register()
3371 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { in rockchip_pinctrl_register()
3372 pdesc->number = k; in rockchip_pinctrl_register()
3373 pdesc->name = pin_names[pin]; in rockchip_pinctrl_register()
3377 INIT_LIST_HEAD(&pin_bank->deferred_pins); in rockchip_pinctrl_register()
3378 mutex_init(&pin_bank->deferred_lock); in rockchip_pinctrl_register()
3385 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); in rockchip_pinctrl_register()
3386 if (IS_ERR(info->pctl_dev)) in rockchip_pinctrl_register()
3387 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); in rockchip_pinctrl_register()
3399 struct device *dev = &pdev->dev; in rockchip_pinctrl_get_soc_data()
3400 struct device_node *node = dev->of_node; in rockchip_pinctrl_get_soc_data()
3407 ctrl = (struct rockchip_pin_ctrl *)match->data; in rockchip_pinctrl_get_soc_data()
3409 grf_offs = ctrl->grf_mux_offset; in rockchip_pinctrl_get_soc_data()
3410 pmu_offs = ctrl->pmu_mux_offset; in rockchip_pinctrl_get_soc_data()
3411 drv_pmu_offs = ctrl->pmu_drv_offset; in rockchip_pinctrl_get_soc_data()
3412 drv_grf_offs = ctrl->grf_drv_offset; in rockchip_pinctrl_get_soc_data()
3413 bank = ctrl->pin_banks; in rockchip_pinctrl_get_soc_data()
3414 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_pinctrl_get_soc_data()
3417 raw_spin_lock_init(&bank->slock); in rockchip_pinctrl_get_soc_data()
3418 bank->drvdata = d; in rockchip_pinctrl_get_soc_data()
3419 bank->pin_base = ctrl->nr_pins; in rockchip_pinctrl_get_soc_data()
3420 ctrl->nr_pins += bank->nr_pins; in rockchip_pinctrl_get_soc_data()
3424 struct rockchip_iomux *iom = &bank->iomux[j]; in rockchip_pinctrl_get_soc_data()
3425 struct rockchip_drv *drv = &bank->drv[j]; in rockchip_pinctrl_get_soc_data()
3428 if (bank_pins >= bank->nr_pins) in rockchip_pinctrl_get_soc_data()
3432 if (iom->offset >= 0) { in rockchip_pinctrl_get_soc_data()
3433 if ((iom->type & IOMUX_SOURCE_PMU) || in rockchip_pinctrl_get_soc_data()
3434 (iom->type & IOMUX_L_SOURCE_PMU)) in rockchip_pinctrl_get_soc_data()
3435 pmu_offs = iom->offset; in rockchip_pinctrl_get_soc_data()
3437 grf_offs = iom->offset; in rockchip_pinctrl_get_soc_data()
3439 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) || in rockchip_pinctrl_get_soc_data()
3440 (iom->type & IOMUX_L_SOURCE_PMU)) ? in rockchip_pinctrl_get_soc_data()
3445 if (drv->offset >= 0) { in rockchip_pinctrl_get_soc_data()
3446 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
3447 drv_pmu_offs = drv->offset; in rockchip_pinctrl_get_soc_data()
3449 drv_grf_offs = drv->offset; in rockchip_pinctrl_get_soc_data()
3451 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? in rockchip_pinctrl_get_soc_data()
3456 i, j, iom->offset, drv->offset); in rockchip_pinctrl_get_soc_data()
3460 * 4bit iomux'es are spread over two registers. in rockchip_pinctrl_get_soc_data()
3462 inc = (iom->type & (IOMUX_WIDTH_4BIT | in rockchip_pinctrl_get_soc_data()
3465 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) in rockchip_pinctrl_get_soc_data()
3472 * 3bit drive-strenth'es are spread over two registers. in rockchip_pinctrl_get_soc_data()
3474 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rockchip_pinctrl_get_soc_data()
3475 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) in rockchip_pinctrl_get_soc_data()
3480 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
3488 /* calculate the per-bank recalced_mask */ in rockchip_pinctrl_get_soc_data()
3489 for (j = 0; j < ctrl->niomux_recalced; j++) { in rockchip_pinctrl_get_soc_data()
3492 if (ctrl->iomux_recalced[j].num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
3493 pin = ctrl->iomux_recalced[j].pin; in rockchip_pinctrl_get_soc_data()
3494 bank->recalced_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()
3498 /* calculate the per-bank route_mask */ in rockchip_pinctrl_get_soc_data()
3499 for (j = 0; j < ctrl->niomux_routes; j++) { in rockchip_pinctrl_get_soc_data()
3502 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
3503 pin = ctrl->iomux_routes[j].pin; in rockchip_pinctrl_get_soc_data()
3504 bank->route_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()
3513 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
3520 int ret = pinctrl_force_sleep(info->pctl_dev); in rockchip_pinctrl_suspend()
3526 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save in rockchip_pinctrl_suspend()
3529 if (info->ctrl->type == RK3288) { in rockchip_pinctrl_suspend()
3530 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, in rockchip_pinctrl_suspend()
3533 pinctrl_force_default(info->pctl_dev); in rockchip_pinctrl_suspend()
3546 if (info->ctrl->type == RK3288) { in rockchip_pinctrl_resume()
3547 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, in rockchip_pinctrl_resume()
3554 return pinctrl_force_default(info->pctl_dev); in rockchip_pinctrl_resume()
3563 struct device *dev = &pdev->dev; in rockchip_pinctrl_probe()
3564 struct device_node *np = dev->of_node, *node; in rockchip_pinctrl_probe()
3570 if (!dev->of_node) in rockchip_pinctrl_probe()
3571 return dev_err_probe(dev, -ENODEV, "device tree node not found\n"); in rockchip_pinctrl_probe()
3575 return -ENOMEM; in rockchip_pinctrl_probe()
3577 info->dev = dev; in rockchip_pinctrl_probe()
3581 return dev_err_probe(dev, -EINVAL, "driver data not available\n"); in rockchip_pinctrl_probe()
3582 info->ctrl = ctrl; in rockchip_pinctrl_probe()
3586 info->regmap_base = syscon_node_to_regmap(node); in rockchip_pinctrl_probe()
3588 if (IS_ERR(info->regmap_base)) in rockchip_pinctrl_probe()
3589 return PTR_ERR(info->regmap_base); in rockchip_pinctrl_probe()
3595 rockchip_regmap_config.max_register = resource_size(res) - 4; in rockchip_pinctrl_probe()
3597 info->regmap_base = in rockchip_pinctrl_probe()
3600 /* to check for the old dt-bindings */ in rockchip_pinctrl_probe()
3601 info->reg_size = resource_size(res); in rockchip_pinctrl_probe()
3604 if (ctrl->type == RK3188 && info->reg_size < 0x200) { in rockchip_pinctrl_probe()
3609 rockchip_regmap_config.max_register = resource_size(res) - 4; in rockchip_pinctrl_probe()
3610 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; in rockchip_pinctrl_probe()
3611 info->regmap_pull = in rockchip_pinctrl_probe()
3619 info->regmap_pmu = syscon_node_to_regmap(node); in rockchip_pinctrl_probe()
3621 if (IS_ERR(info->regmap_pmu)) in rockchip_pinctrl_probe()
3622 return PTR_ERR(info->regmap_pmu); in rockchip_pinctrl_probe()
3631 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); in rockchip_pinctrl_probe()
3645 of_platform_depopulate(&pdev->dev); in rockchip_pinctrl_remove()
3647 for (i = 0; i < info->ctrl->nr_banks; i++) { in rockchip_pinctrl_remove()
3648 bank = &info->ctrl->pin_banks[i]; in rockchip_pinctrl_remove()
3650 mutex_lock(&bank->deferred_lock); in rockchip_pinctrl_remove()
3651 while (!list_empty(&bank->deferred_pins)) { in rockchip_pinctrl_remove()
3652 cfg = list_first_entry(&bank->deferred_pins, in rockchip_pinctrl_remove()
3654 list_del(&cfg->head); in rockchip_pinctrl_remove()
3657 mutex_unlock(&bank->deferred_lock); in rockchip_pinctrl_remove()
3687 .label = "PX30-GPIO",
3711 .label = "RV1108-GPIO",
3751 .label = "RV1126-GPIO",
3753 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
3774 .label = "RK2928-GPIO",
3789 .label = "RK3036-GPIO",
3807 .label = "RK3066a-GPIO",
3823 .label = "RK3066b-GPIO",
3838 .label = "RK3128-GPIO",
3858 .label = "RK3188-GPIO",
3876 .label = "RK3228-GPIO",
3920 .label = "RK3288-GPIO",
3956 .label = "RK3308-GPIO",
3985 .label = "RK3328-GPIO",
4011 .label = "RK3368-GPIO",
4031 -1,
4032 -1,
4075 .label = "RK3399-GPIO",
4113 .label = "RK3568-GPIO",
4150 .label = "RK3576-GPIO",
4173 .label = "RK3588-GPIO",
4181 { .compatible = "rockchip,px30-pinctrl",
4183 { .compatible = "rockchip,rv1108-pinctrl",
4185 { .compatible = "rockchip,rv1126-pinctrl",
4187 { .compatible = "rockchip,rk2928-pinctrl",
4189 { .compatible = "rockchip,rk3036-pinctrl",
4191 { .compatible = "rockchip,rk3066a-pinctrl",
4193 { .compatible = "rockchip,rk3066b-pinctrl",
4195 { .compatible = "rockchip,rk3128-pinctrl",
4197 { .compatible = "rockchip,rk3188-pinctrl",
4199 { .compatible = "rockchip,rk3228-pinctrl",
4201 { .compatible = "rockchip,rk3288-pinctrl",
4203 { .compatible = "rockchip,rk3308-pinctrl",
4205 { .compatible = "rockchip,rk3328-pinctrl",
4207 { .compatible = "rockchip,rk3368-pinctrl",
4209 { .compatible = "rockchip,rk3399-pinctrl",
4211 { .compatible = "rockchip,rk3568-pinctrl",
4213 { .compatible = "rockchip,rk3576-pinctrl",
4215 { .compatible = "rockchip,rk3588-pinctrl",
4224 .name = "rockchip-pinctrl",
4244 MODULE_ALIAS("platform:pinctrl-rockchip");