Lines Matching +full:function +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/pinctrl/pinconf-generic.h>
23 #include <asm/mach-pic32/pic32.h>
25 #include "pinctrl-utils.h"
26 #include "pinctrl-pic32.h"
271 #define FUNCTION(_name, _gr) \ macro
279 FUNCTION(INT3, input0),
280 FUNCTION(T2CK, input0),
281 FUNCTION(T6CK, input0),
282 FUNCTION(IC3, input0),
283 FUNCTION(IC7, input0),
284 FUNCTION(U1RX, input0),
285 FUNCTION(U2CTS, input0),
286 FUNCTION(U5RX, input0),
287 FUNCTION(U6CTS, input0),
288 FUNCTION(SDI1, input0),
289 FUNCTION(SDI3, input0),
290 FUNCTION(SDI5, input0),
291 FUNCTION(SS6IN, input0),
292 FUNCTION(REFCLKI1, input0),
293 FUNCTION(INT4, input1),
294 FUNCTION(T5CK, input1),
295 FUNCTION(T7CK, input1),
296 FUNCTION(IC4, input1),
297 FUNCTION(IC8, input1),
298 FUNCTION(U3RX, input1),
299 FUNCTION(U4CTS, input1),
300 FUNCTION(SDI2, input1),
301 FUNCTION(SDI4, input1),
302 FUNCTION(C1RX, input1),
303 FUNCTION(REFCLKI4, input1),
304 FUNCTION(INT2, input2),
305 FUNCTION(T3CK, input2),
306 FUNCTION(T8CK, input2),
307 FUNCTION(IC2, input2),
308 FUNCTION(IC5, input2),
309 FUNCTION(IC9, input2),
310 FUNCTION(U1CTS, input2),
311 FUNCTION(U2RX, input2),
312 FUNCTION(U5CTS, input2),
313 FUNCTION(SS1IN, input2),
314 FUNCTION(SS3IN, input2),
315 FUNCTION(SS4IN, input2),
316 FUNCTION(SS5IN, input2),
317 FUNCTION(C2RX, input2),
318 FUNCTION(INT1, input3),
319 FUNCTION(T4CK, input3),
320 FUNCTION(T9CK, input3),
321 FUNCTION(IC1, input3),
322 FUNCTION(IC6, input3),
323 FUNCTION(U3CTS, input3),
324 FUNCTION(U4RX, input3),
325 FUNCTION(U6RX, input3),
326 FUNCTION(SS2IN, input3),
327 FUNCTION(SDI6, input3),
328 FUNCTION(OCFA, input3),
329 FUNCTION(REFCLKI3, input3),
330 FUNCTION(U3TX, output0),
331 FUNCTION(U4RTS, output0),
332 FUNCTION(SDO1, output0_1),
333 FUNCTION(SDO2, output0_1),
334 FUNCTION(SDO3, output0_1),
335 FUNCTION(SDO5, output0_1),
336 FUNCTION(SS6OUT, output0),
337 FUNCTION(OC3, output0),
338 FUNCTION(OC6, output0),
339 FUNCTION(REFCLKO4, output0),
340 FUNCTION(C2OUT, output0),
341 FUNCTION(C1TX, output0),
342 FUNCTION(U1TX, output1),
343 FUNCTION(U2RTS, output1),
344 FUNCTION(U5TX, output1),
345 FUNCTION(U6RTS, output1),
346 FUNCTION(SDO4, output1_3),
347 FUNCTION(OC4, output1),
348 FUNCTION(OC7, output1),
349 FUNCTION(REFCLKO1, output1),
350 FUNCTION(U3RTS, output2),
351 FUNCTION(U4TX, output2),
352 FUNCTION(U6TX, output2_3),
353 FUNCTION(SS1OUT, output2),
354 FUNCTION(SS3OUT, output2),
355 FUNCTION(SS4OUT, output2),
356 FUNCTION(SS5OUT, output2),
357 FUNCTION(SDO6, output2_3),
358 FUNCTION(OC5, output2),
359 FUNCTION(OC8, output2),
360 FUNCTION(C1OUT, output2),
361 FUNCTION(REFCLKO3, output2),
362 FUNCTION(U1RTS, output3),
363 FUNCTION(U2TX, output3),
364 FUNCTION(U5RTS, output3),
365 FUNCTION(SS2OUT, output3),
366 FUNCTION(OC2, output3),
367 FUNCTION(OC1, output3),
368 FUNCTION(OC9, output3),
369 FUNCTION(C2TX, output3),
1702 return &pctl->gpio_banks[pin / PINS_PER_BANK]; in pctl_to_bank()
1709 return pctl->ngroups; in pic32_pinctrl_get_groups_count()
1717 return pctl->groups[group].name; in pic32_pinctrl_get_group_name()
1727 *pins = &pctl->groups[group].pin; in pic32_pinctrl_get_group_pins()
1745 return pctl->nfunctions; in pic32_pinmux_get_functions_count()
1753 return pctl->functions[func].name; in pic32_pinmux_get_function_name()
1763 *groups = pctl->functions[func].groups; in pic32_pinmux_get_function_groups()
1764 *num_groups = pctl->functions[func].ngroups; in pic32_pinmux_get_function_groups()
1773 const struct pic32_pin_group *pg = &pctl->groups[group]; in pic32_pinmux_enable()
1774 const struct pic32_function *pf = &pctl->functions[func]; in pic32_pinmux_enable()
1775 const char *fname = pf->name; in pic32_pinmux_enable()
1776 struct pic32_desc_function *functions = pg->functions; in pic32_pinmux_enable()
1778 while (functions->name) { in pic32_pinmux_enable()
1779 if (!strcmp(functions->name, fname)) { in pic32_pinmux_enable()
1780 dev_dbg(pctl->dev, in pic32_pinmux_enable()
1781 "setting function %s reg 0x%x = %d\n", in pic32_pinmux_enable()
1782 fname, functions->muxreg, functions->muxval); in pic32_pinmux_enable()
1784 writel(functions->muxval, pctl->reg_base + functions->muxreg); in pic32_pinmux_enable()
1792 dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func); in pic32_pinmux_enable()
1794 return -EINVAL; in pic32_pinmux_enable()
1802 struct pic32_gpio_bank *bank = gpiochip_get_data(range->gc); in pic32_gpio_request_enable()
1803 u32 mask = BIT(offset - bank->gpio_chip.base); in pic32_gpio_request_enable() local
1805 dev_dbg(pctl->dev, "requesting gpio %d in bank %d with mask 0x%x\n", in pic32_gpio_request_enable()
1806 offset, bank->gpio_chip.base, mask); in pic32_gpio_request_enable()
1808 writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG)); in pic32_gpio_request_enable()
1817 u32 mask = BIT(offset); in pic32_gpio_direction_input() local
1819 writel(mask, bank->reg_base + PIC32_SET(TRIS_REG)); in pic32_gpio_direction_input()
1828 return !!(readl(bank->reg_base + PORT_REG) & BIT(offset)); in pic32_gpio_get()
1835 u32 mask = BIT(offset); in pic32_gpio_set() local
1838 writel(mask, bank->reg_base + PIC32_SET(PORT_REG)); in pic32_gpio_set()
1840 writel(mask, bank->reg_base + PIC32_CLR(PORT_REG)); in pic32_gpio_set()
1847 u32 mask = BIT(offset); in pic32_gpio_direction_output() local
1850 writel(mask, bank->reg_base + PIC32_CLR(TRIS_REG)); in pic32_gpio_direction_output()
1859 struct gpio_chip *chip = range->gc; in pic32_gpio_set_direction()
1884 u32 mask = BIT(pin - bank->gpio_chip.base); in pic32_pinconf_get() local
1889 arg = !!(readl(bank->reg_base + CNPU_REG) & mask); in pic32_pinconf_get()
1892 arg = !!(readl(bank->reg_base + CNPD_REG) & mask); in pic32_pinconf_get()
1895 arg = !(readl(bank->reg_base + ANSEL_REG) & mask); in pic32_pinconf_get()
1898 arg = !!(readl(bank->reg_base + ANSEL_REG) & mask); in pic32_pinconf_get()
1901 arg = !!(readl(bank->reg_base + ODCU_REG) & mask); in pic32_pinconf_get()
1904 arg = !!(readl(bank->reg_base + TRIS_REG) & mask); in pic32_pinconf_get()
1907 arg = !(readl(bank->reg_base + TRIS_REG) & mask); in pic32_pinconf_get()
1910 dev_err(pctl->dev, "Property %u not supported\n", param); in pic32_pinconf_get()
1911 return -ENOTSUPP; in pic32_pinconf_get()
1927 u32 offset = pin - bank->gpio_chip.base; in pic32_pinconf_set()
1928 u32 mask = BIT(offset); in pic32_pinconf_set() local
1930 dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n", in pic32_pinconf_set()
1931 pin, bank->gpio_chip.base, mask); in pic32_pinconf_set()
1939 dev_dbg(pctl->dev, " pullup\n"); in pic32_pinconf_set()
1940 writel(mask, bank->reg_base +PIC32_SET(CNPU_REG)); in pic32_pinconf_set()
1943 dev_dbg(pctl->dev, " pulldown\n"); in pic32_pinconf_set()
1944 writel(mask, bank->reg_base + PIC32_SET(CNPD_REG)); in pic32_pinconf_set()
1947 dev_dbg(pctl->dev, " digital\n"); in pic32_pinconf_set()
1948 writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG)); in pic32_pinconf_set()
1951 dev_dbg(pctl->dev, " analog\n"); in pic32_pinconf_set()
1952 writel(mask, bank->reg_base + PIC32_SET(ANSEL_REG)); in pic32_pinconf_set()
1955 dev_dbg(pctl->dev, " opendrain\n"); in pic32_pinconf_set()
1956 writel(mask, bank->reg_base + PIC32_SET(ODCU_REG)); in pic32_pinconf_set()
1959 pic32_gpio_direction_input(&bank->gpio_chip, offset); in pic32_pinconf_set()
1962 pic32_gpio_direction_output(&bank->gpio_chip, in pic32_pinconf_set()
1966 dev_err(pctl->dev, "Property %u not supported\n", in pic32_pinconf_set()
1968 return -ENOTSUPP; in pic32_pinconf_set()
1982 .name = "pic32-pinctrl",
1993 if (readl(bank->reg_base + TRIS_REG) & BIT(offset)) in pic32_gpio_get_direction()
2003 writel(0, bank->reg_base + CNF_REG); in pic32_gpio_irq_ack()
2010 writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_CLR(CNCON_REG)); in pic32_gpio_irq_mask()
2011 gpiochip_disable_irq(&bank->gpio_chip, irqd_to_hwirq(data)); in pic32_gpio_irq_mask()
2018 gpiochip_enable_irq(&bank->gpio_chip, irqd_to_hwirq(data)); in pic32_gpio_irq_unmask()
2019 writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_SET(CNCON_REG)); in pic32_gpio_irq_unmask()
2026 pic32_gpio_direction_input(chip, data->hwirq); in pic32_gpio_irq_startup()
2035 u32 mask = irqd_to_hwirq(data); in pic32_gpio_irq_set_type() local
2040 writel(mask, bank->reg_base + PIC32_SET(CNEN_REG)); in pic32_gpio_irq_set_type()
2042 writel(mask, bank->reg_base + PIC32_CLR(CNNE_REG)); in pic32_gpio_irq_set_type()
2044 writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); in pic32_gpio_irq_set_type()
2048 writel(mask, bank->reg_base + PIC32_CLR(CNEN_REG)); in pic32_gpio_irq_set_type()
2050 writel(mask, bank->reg_base + PIC32_SET(CNNE_REG)); in pic32_gpio_irq_set_type()
2052 writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); in pic32_gpio_irq_set_type()
2056 writel(mask, bank->reg_base + PIC32_SET(CNEN_REG)); in pic32_gpio_irq_set_type()
2058 writel(mask, bank->reg_base + PIC32_SET(CNNE_REG)); in pic32_gpio_irq_set_type()
2060 writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); in pic32_gpio_irq_set_type()
2063 return -EINVAL; in pic32_gpio_irq_set_type()
2078 cnen_rise = readl(bank->reg_base + CNEN_REG); in pic32_gpio_get_pending()
2079 cnne_fall = readl(bank->reg_base + CNNE_REG); in pic32_gpio_get_pending()
2082 u32 mask = BIT(pin); in pic32_gpio_get_pending() local
2084 if ((mask & cnen_rise) || (mask && cnne_fall)) in pic32_gpio_get_pending()
2085 pending |= mask; in pic32_gpio_get_pending()
2102 stat = readl(bank->reg_base + CNF_REG); in pic32_gpio_irq_handler()
2106 generic_handle_domain_irq(gc->irq.domain, pin); in pic32_gpio_irq_handler()
2147 seq_printf(p, "GPIO%d", bank->instance); in pic32_gpio_irq_print_chip()
2166 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); in pic32_pinctrl_probe()
2168 return -ENOMEM; in pic32_pinctrl_probe()
2169 pctl->dev = &pdev->dev; in pic32_pinctrl_probe()
2170 dev_set_drvdata(&pdev->dev, pctl); in pic32_pinctrl_probe()
2172 pctl->reg_base = devm_platform_ioremap_resource(pdev, 0); in pic32_pinctrl_probe()
2173 if (IS_ERR(pctl->reg_base)) in pic32_pinctrl_probe()
2174 return PTR_ERR(pctl->reg_base); in pic32_pinctrl_probe()
2176 pctl->clk = devm_clk_get(&pdev->dev, NULL); in pic32_pinctrl_probe()
2177 if (IS_ERR(pctl->clk)) { in pic32_pinctrl_probe()
2178 ret = PTR_ERR(pctl->clk); in pic32_pinctrl_probe()
2179 dev_err(&pdev->dev, "clk get failed\n"); in pic32_pinctrl_probe()
2183 ret = clk_prepare_enable(pctl->clk); in pic32_pinctrl_probe()
2185 dev_err(&pdev->dev, "clk enable failed\n"); in pic32_pinctrl_probe()
2189 pctl->pins = pic32_pins; in pic32_pinctrl_probe()
2190 pctl->npins = ARRAY_SIZE(pic32_pins); in pic32_pinctrl_probe()
2191 pctl->functions = pic32_functions; in pic32_pinctrl_probe()
2192 pctl->nfunctions = ARRAY_SIZE(pic32_functions); in pic32_pinctrl_probe()
2193 pctl->groups = pic32_groups; in pic32_pinctrl_probe()
2194 pctl->ngroups = ARRAY_SIZE(pic32_groups); in pic32_pinctrl_probe()
2195 pctl->gpio_banks = pic32_gpio_banks; in pic32_pinctrl_probe()
2196 pctl->nbanks = ARRAY_SIZE(pic32_gpio_banks); in pic32_pinctrl_probe()
2198 pic32_pinctrl_desc.pins = pctl->pins; in pic32_pinctrl_probe()
2199 pic32_pinctrl_desc.npins = pctl->npins; in pic32_pinctrl_probe()
2203 pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pic32_pinctrl_desc, in pic32_pinctrl_probe()
2205 if (IS_ERR(pctl->pctldev)) { in pic32_pinctrl_probe()
2206 dev_err(&pdev->dev, "Failed to register pinctrl device\n"); in pic32_pinctrl_probe()
2207 return PTR_ERR(pctl->pctldev); in pic32_pinctrl_probe()
2215 struct device_node *np = pdev->dev.of_node; in pic32_gpio_probe()
2221 if (of_property_read_u32(np, "microchip,gpio-bank", &id)) { in pic32_gpio_probe()
2222 dev_err(&pdev->dev, "microchip,gpio-bank property not found\n"); in pic32_gpio_probe()
2223 return -EINVAL; in pic32_gpio_probe()
2227 dev_err(&pdev->dev, "invalid microchip,gpio-bank property\n"); in pic32_gpio_probe()
2228 return -EINVAL; in pic32_gpio_probe()
2233 bank->reg_base = devm_platform_ioremap_resource(pdev, 0); in pic32_gpio_probe()
2234 if (IS_ERR(bank->reg_base)) in pic32_gpio_probe()
2235 return PTR_ERR(bank->reg_base); in pic32_gpio_probe()
2241 bank->clk = devm_clk_get(&pdev->dev, NULL); in pic32_gpio_probe()
2242 if (IS_ERR(bank->clk)) { in pic32_gpio_probe()
2243 ret = PTR_ERR(bank->clk); in pic32_gpio_probe()
2244 dev_err(&pdev->dev, "clk get failed\n"); in pic32_gpio_probe()
2248 ret = clk_prepare_enable(bank->clk); in pic32_gpio_probe()
2250 dev_err(&pdev->dev, "clk enable failed\n"); in pic32_gpio_probe()
2254 bank->gpio_chip.parent = &pdev->dev; in pic32_gpio_probe()
2256 girq = &bank->gpio_chip.irq; in pic32_gpio_probe()
2258 girq->parent_handler = pic32_gpio_irq_handler; in pic32_gpio_probe()
2259 girq->num_parents = 1; in pic32_gpio_probe()
2260 girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), in pic32_gpio_probe()
2262 if (!girq->parents) in pic32_gpio_probe()
2263 return -ENOMEM; in pic32_gpio_probe()
2264 girq->default_type = IRQ_TYPE_NONE; in pic32_gpio_probe()
2265 girq->handler = handle_level_irq; in pic32_gpio_probe()
2266 girq->parents[0] = irq; in pic32_gpio_probe()
2267 ret = gpiochip_add_data(&bank->gpio_chip, bank); in pic32_gpio_probe()
2269 dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n", in pic32_gpio_probe()
2277 { .compatible = "microchip,pic32mzda-pinctrl", },
2283 .name = "pic32-pinctrl",
2291 { .compatible = "microchip,pic32mzda-gpio", },
2297 .name = "pic32-gpio",