Lines Matching +full:ras +full:- +full:to +full:- +full:cas
6 * This is a group-only pin controller.
19 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
26 #define DRIVER_NAME "pinctrl-gemini"
29 * struct gemini_pin_conf - information about configuring a pin
41 * struct gemini_pmx - state holder for the gemini pin controller
42 * @dev: a pointer back to containing device
43 * @virtbase: the offset to the controller in virtual memory
44 * @map: regmap to access registers
64 * struct gemini_pin_group - describes a Gemini pin group
67 * from the driver-local pin enumeration space
70 * @mask: bits to clear to enable this when doing pin muxing
71 * @value: bits to set to enable this when doing pin muxing
85 /* Some straight-forward control registers */
98 * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot
101 * - For the bits named *_DISABLE, once you enable something, it cannot be
200 PINCTRL_PIN(46, "C11 DRAM CAS N"),
219 PINCTRL_PIN(64, "D11 DRAM RAS N"),
552 * PCI needs to be active at the same time.
586 305, /* UART_NRTS RTS request to send */
587 287, /* UART_NCTS CTS clear to send */
612 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
620 * The parallel flash can be set up in a 26-bit address bus mode exposing
621 * A[0-15] (A[15] takes the place of ALE), but it has the
640 /* The GPIO0B (1-4) pins overlap with TVC and ICE */
643 /* The GPIO0C (5-7) pins overlap with ICE */
649 /* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */
670 /* The GPIO0L (26-29) pins overlap with parallel flash */
676 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
679 /* The GPIO1B (5-10, 27) pins overlap with just IDE */
684 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
690 /* The GPIO1D (28-31) pins overlap with LCD and TVC */
693 /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
696 /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
699 /* The GPIO2C (8-31) pins overlap with PCI */
840 * The construction is done such that it is possible to use a serial
842 * possible to use NAND and parallel flash together. To use serial
843 * flash with one of the two others, the muxbits need to be flipped
1095 PINCTRL_PIN(74, "D15 DRAM RAS N"),
1501 * PCI needs to be active at the same time.
1535 398, /* UART_NRTS RTS request to send */
1536 316, /* UART_NCTS CTS clear to send */
1561 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
1569 * The parallel flash can be set up in a 26-bit address bus mode exposing
1570 * A[0-15] (A[15] takes the place of ALE), but it has the
1586 /* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */
1589 /* The GPIO0B (5-7) pins overlap with ICE */
1592 /* The GPIO0C (8,11-15) pins overlap with LPC, UART and SSP */
1604 /* The GPIO0G (19,20,26-29) pins overlap with parallel flash */
1622 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
1625 /* The GPIO1B (5-10,27) pins overlap with just IDE */
1628 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
1634 /* The GPIO1D (28-31) pins overlap with TVC */
1637 /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
1640 /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
1643 /* The GPIO2C (8-31) pins overlap with PCI */
1790 * The construction is done such that it is possible to use a serial
1792 * possible to use NAND and parallel flash together. To use serial
1793 * flash with one of the two others, the muxbits need to be flipped
1962 if (pmx->is_3512) in gemini_get_groups_count()
1964 if (pmx->is_3516) in gemini_get_groups_count()
1974 if (pmx->is_3512) in gemini_get_group_name()
1976 if (pmx->is_3516) in gemini_get_group_name()
1989 if (pmx->flash_pin && in gemini_get_group_pins()
1990 pmx->is_3512 && in gemini_get_group_pins()
1996 if (pmx->flash_pin && in gemini_get_group_pins()
1997 pmx->is_3516 && in gemini_get_group_pins()
2003 if (pmx->is_3512) { in gemini_get_group_pins()
2007 if (pmx->is_3516) { in gemini_get_group_pins()
2030 * struct gemini_pmx_func - describes Gemini pinmux functions
2203 if (pmx->is_3512) in gemini_pmx_set_mux()
2205 else if (pmx->is_3516) in gemini_pmx_set_mux()
2208 dev_err(pmx->dev, "invalid SoC type\n"); in gemini_pmx_set_mux()
2209 return -ENODEV; in gemini_pmx_set_mux()
2212 dev_dbg(pmx->dev, in gemini_pmx_set_mux()
2214 func->name, grp->name); in gemini_pmx_set_mux()
2216 regmap_read(pmx->map, GLOBAL_MISC_CTRL, &before); in gemini_pmx_set_mux()
2217 regmap_update_bits(pmx->map, GLOBAL_MISC_CTRL, in gemini_pmx_set_mux()
2218 grp->mask | grp->value, in gemini_pmx_set_mux()
2219 grp->value); in gemini_pmx_set_mux()
2220 regmap_read(pmx->map, GLOBAL_MISC_CTRL, &after); in gemini_pmx_set_mux()
2225 expected = before &= ~grp->mask; in gemini_pmx_set_mux()
2226 expected |= grp->value; in gemini_pmx_set_mux()
2230 tmp = grp->mask; in gemini_pmx_set_mux()
2236 dev_err(pmx->dev, in gemini_pmx_set_mux()
2241 dev_err(pmx->dev, in gemini_pmx_set_mux()
2245 dev_dbg(pmx->dev, in gemini_pmx_set_mux()
2252 tmp = grp->value; in gemini_pmx_set_mux()
2258 dev_err(pmx->dev, in gemini_pmx_set_mux()
2263 dev_err(pmx->dev, in gemini_pmx_set_mux()
2267 dev_dbg(pmx->dev, in gemini_pmx_set_mux()
2371 for (i = 0; i < pmx->nconfs; i++) { in gemini_get_pin_conf()
2372 retconf = &pmx->confs[i]; in gemini_get_pin_conf()
2373 if (retconf->pin == pin) in gemini_get_pin_conf()
2391 return -ENOTSUPP; in gemini_pinconf_get()
2392 regmap_read(pmx->map, conf->reg, &val); in gemini_pinconf_get()
2393 val &= conf->mask; in gemini_pinconf_get()
2394 val >>= (ffs(conf->mask) - 1); in gemini_pinconf_get()
2398 return -ENOTSUPP; in gemini_pinconf_get()
2421 return -EINVAL; in gemini_pinconf_set()
2424 dev_err(pmx->dev, in gemini_pinconf_set()
2426 return -ENOTSUPP; in gemini_pinconf_set()
2428 arg <<= (ffs(conf->mask) - 1); in gemini_pinconf_set()
2429 dev_dbg(pmx->dev, in gemini_pinconf_set()
2430 "set pin %d to skew delay mask %08x, val %08x\n", in gemini_pinconf_set()
2431 pin, conf->mask, arg); in gemini_pinconf_set()
2432 regmap_update_bits(pmx->map, conf->reg, conf->mask, arg); in gemini_pinconf_set()
2435 dev_err(pmx->dev, "Invalid config param %04x\n", param); in gemini_pinconf_set()
2436 return -ENOTSUPP; in gemini_pinconf_set()
2455 if (pmx->is_3512) in gemini_pinconf_group_set()
2457 if (pmx->is_3516) in gemini_pinconf_group_set()
2461 if (!grp->driving_mask) { in gemini_pinconf_group_set()
2462 dev_err(pmx->dev, "pin config group \"%s\" does " in gemini_pinconf_group_set()
2464 grp->name); in gemini_pinconf_group_set()
2465 return -EINVAL; in gemini_pinconf_group_set()
2488 dev_err(pmx->dev, in gemini_pinconf_group_set()
2491 return -ENOTSUPP; in gemini_pinconf_group_set()
2493 val <<= (ffs(grp->driving_mask) - 1); in gemini_pinconf_group_set()
2494 regmap_update_bits(pmx->map, GLOBAL_IODRIVE, in gemini_pinconf_group_set()
2495 grp->driving_mask, in gemini_pinconf_group_set()
2497 dev_dbg(pmx->dev, in gemini_pinconf_group_set()
2498 "set group %s to %d mA drive strength mask %08x val %08x\n", in gemini_pinconf_group_set()
2499 grp->name, arg, grp->driving_mask, val); in gemini_pinconf_group_set()
2502 dev_err(pmx->dev, "invalid config param %04x\n", param); in gemini_pinconf_group_set()
2503 return -ENOTSUPP; in gemini_pinconf_group_set()
2529 struct device *dev = &pdev->dev; in gemini_pmx_probe()
2537 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); in gemini_pmx_probe()
2539 return -ENOMEM; in gemini_pmx_probe()
2541 pmx->dev = &pdev->dev; in gemini_pmx_probe()
2542 parent = dev->parent; in gemini_pmx_probe()
2544 dev_err(dev, "no parent to pin controller\n"); in gemini_pmx_probe()
2545 return -ENODEV; in gemini_pmx_probe()
2547 map = syscon_node_to_regmap(parent->of_node); in gemini_pmx_probe()
2552 pmx->map = map; in gemini_pmx_probe()
2563 pmx->is_3512 = true; in gemini_pmx_probe()
2564 pmx->confs = gemini_confs_3512; in gemini_pmx_probe()
2565 pmx->nconfs = ARRAY_SIZE(gemini_confs_3512); in gemini_pmx_probe()
2570 pmx->is_3516 = true; in gemini_pmx_probe()
2571 pmx->confs = gemini_confs_3516; in gemini_pmx_probe()
2572 pmx->nconfs = ARRAY_SIZE(gemini_confs_3516); in gemini_pmx_probe()
2578 return -ENODEV; in gemini_pmx_probe()
2596 pmx->flash_pin = !!(val & GLOBAL_STATUS_FLPIN); in gemini_pmx_probe()
2597 dev_info(dev, "flash pin is %s\n", pmx->flash_pin ? "set" : "not set"); in gemini_pmx_probe()
2599 pmx->pctl = devm_pinctrl_register(dev, &gemini_pmx_desc, pmx); in gemini_pmx_probe()
2600 if (IS_ERR(pmx->pctl)) { in gemini_pmx_probe()
2602 return PTR_ERR(pmx->pctl); in gemini_pmx_probe()
2611 { .compatible = "cortina,gemini-pinctrl" },