1 // SPDX-License-Identifier: GPL-2.0-only
5  * The registers are located in a syscon region called OLB. There are two pin
7  * pull-down, pull-up, drive strength and muxing.
10  * that is pin-dependent. Functions are declared statically in this driver.
15  * We use eq5p_ as prefix, as-in "EyeQ5 Pinctrl", but way shorter.
33 #include <linux/pinctrl/pinconf-generic.h>
39 #include "pinctrl-utils.h"
201 static void eq5p_update_bits(const struct eq5p_pinctrl *pctrl,  in eq5p_update_bits()  argument
205 	void __iomem *ptr = pctrl->base + eq5p_regs[bank][reg];  in eq5p_update_bits()
210 static bool eq5p_test_bit(const struct eq5p_pinctrl *pctrl,  in eq5p_test_bit()  argument
213 	u32 val = readl(pctrl->base + eq5p_regs[bank][reg]);  in eq5p_test_bit()
234 		return pin - EQ5P_PIN_OFFSET_BANK_B;  in eq5p_pin_to_offset()
245 	return pctldev->desc->pins[selector].name;  in eq5p_pinctrl_get_group_name()
253 	*pins = &pctldev->desc->pins[selector].number;  in eq5p_pinctrl_get_group_pins()
262 	struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in eq5p_pinconf_get()  local
268 	pd = eq5p_test_bit(pctrl, bank, EQ5P_PD, offset);  in eq5p_pinconf_get()
269 	pu = eq5p_test_bit(pctrl, bank, EQ5P_PU, offset);  in eq5p_pinconf_get()
284 			val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_HIGH]);  in eq5p_pinconf_get()
285 			offset -= 32;  in eq5p_pinconf_get()
287 			val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_LOW]);  in eq5p_pinconf_get()
292 		return -ENOTSUPP;  in eq5p_pinconf_get()
303 	struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in eq5p_pinctrl_pin_dbg_show()  local
304 	const char *pin_name = pctrl->desc.pins[pin].name;  in eq5p_pinctrl_pin_dbg_show()
317 	if (eq5p_test_bit(pctrl, bank, EQ5P_IOCR, offset)) {  in eq5p_pinctrl_pin_dbg_show()
348 	pd = eq5p_test_bit(pctrl, bank, EQ5P_PD, offset);  in eq5p_pinctrl_pin_dbg_show()
349 	pu = eq5p_test_bit(pctrl, bank, EQ5P_PU, offset);  in eq5p_pinctrl_pin_dbg_show()
401 	struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in eq5p_pinmux_set_mux()  local
403 	const char *group_name = pctldev->desc->pins[pin].name;  in eq5p_pinmux_set_mux()
409 	dev_dbg(pctldev->dev, "func=%s group=%s\n", func_name, group_name);  in eq5p_pinmux_set_mux()
413 	eq5p_update_bits(pctrl, bank, EQ5P_IOCR, mask, val);  in eq5p_pinmux_set_mux()
437 	struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in eq5p_pinconf_set_drive_strength()  local
444 		dev_err(pctldev->dev, "Unsupported drive strength: %u\n", arg);  in eq5p_pinconf_set_drive_strength()
445 		return -EINVAL;  in eq5p_pinconf_set_drive_strength()
452 		offset -= 32;  in eq5p_pinconf_set_drive_strength()
459 	eq5p_update_bits(pctrl, bank, reg, mask, val);  in eq5p_pinconf_set_drive_strength()
466 	struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in eq5p_pinconf_set()  local
467 	const char *pin_name = pctldev->desc->pins[pin].name;  in eq5p_pinconf_set()
470 	struct device *dev = pctldev->dev;  in eq5p_pinconf_set()
482 			eq5p_update_bits(pctrl, bank, EQ5P_PD, val, 0);  in eq5p_pinconf_set()
483 			eq5p_update_bits(pctrl, bank, EQ5P_PU, val, 0);  in eq5p_pinconf_set()
491 				return -ENOTSUPP;  in eq5p_pinconf_set()
493 			eq5p_update_bits(pctrl, bank, EQ5P_PD, val, val);  in eq5p_pinconf_set()
494 			eq5p_update_bits(pctrl, bank, EQ5P_PU, val, 0);  in eq5p_pinconf_set()
502 				return -ENOTSUPP;  in eq5p_pinconf_set()
504 			eq5p_update_bits(pctrl, bank, EQ5P_PD, val, 0);  in eq5p_pinconf_set()
505 			eq5p_update_bits(pctrl, bank, EQ5P_PU, val, val);  in eq5p_pinconf_set()
517 			return -ENOTSUPP;  in eq5p_pinconf_set()
536 	struct device *dev = &adev->dev;  in eq5p_probe()
538 	struct eq5p_pinctrl *pctrl;  in eq5p_probe()  local
541 	pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);  in eq5p_probe()
542 	if (!pctrl)  in eq5p_probe()
543 		return -ENOMEM;  in eq5p_probe()
545 	pctrl->base = (void __iomem *)dev_get_platdata(dev);  in eq5p_probe()
546 	pctrl->desc.name = dev_name(dev);  in eq5p_probe()
547 	pctrl->desc.pins = eq5p_pins;  in eq5p_probe()
548 	pctrl->desc.npins = ARRAY_SIZE(eq5p_pins);  in eq5p_probe()
549 	pctrl->desc.pctlops = &eq5p_pinctrl_ops;  in eq5p_probe()
550 	pctrl->desc.pmxops = &eq5p_pinmux_ops;  in eq5p_probe()
551 	pctrl->desc.confops = &eq5p_pinconf_ops;  in eq5p_probe()
552 	pctrl->desc.owner = THIS_MODULE;  in eq5p_probe()
554 	ret = devm_pinctrl_register_and_init(dev, &pctrl->desc, pctrl, &pctldev);  in eq5p_probe()