Lines Matching +full:bank +full:- +full:number
1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/pinctrl/at91.h>
21 #include <linux/pinctrl/pinconf-generic.h>
28 #include "pinctrl-utils.h"
34 * designed the pin id into this bank.
80 * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
81 * @nbanks: number of PIO banks
82 * @last_bank_count: number of lines in the last bank (can be less than
101 unsigned int bank; member
107 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
110 * @nbanks: number of PIO groups, it can vary depending on the SoC.
115 * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
118 * @npins: number of pins.
121 * @irqs: table containing the hw irq number of the bank. The index of the
122 * table is the bank id.
157 {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
160 /* --- GPIO --- */
162 unsigned int bank, unsigned int reg) in atmel_gpio_read() argument
164 return readl_relaxed(atmel_pioctrl->reg_base in atmel_gpio_read()
165 + ATMEL_PIO_BANK_OFFSET * bank + reg); in atmel_gpio_read()
169 unsigned int bank, unsigned int reg, in atmel_gpio_write() argument
172 writel_relaxed(val, atmel_pioctrl->reg_base in atmel_gpio_write()
173 + ATMEL_PIO_BANK_OFFSET * bank + reg); in atmel_gpio_write()
187 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; in atmel_gpio_irq_set_type()
190 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, in atmel_gpio_irq_set_type()
191 BIT(pin->line)); in atmel_gpio_irq_set_type()
192 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); in atmel_gpio_irq_set_type()
218 return -EINVAL; in atmel_gpio_irq_set_type()
221 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); in atmel_gpio_irq_set_type()
229 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; in atmel_gpio_irq_mask()
231 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR, in atmel_gpio_irq_mask()
232 BIT(pin->line)); in atmel_gpio_irq_mask()
238 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; in atmel_gpio_irq_unmask()
240 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER, in atmel_gpio_irq_unmask()
241 BIT(pin->line)); in atmel_gpio_irq_unmask()
247 int bank = ATMEL_PIO_BANK(d->hwirq); in atmel_gpio_irq_set_wake() local
248 int line = ATMEL_PIO_LINE(d->hwirq); in atmel_gpio_irq_set_wake()
250 /* The gpio controller has one interrupt line per bank. */ in atmel_gpio_irq_set_wake()
251 irq_set_irq_wake(atmel_pioctrl->irqs[bank], on); in atmel_gpio_irq_set_wake()
254 atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line); in atmel_gpio_irq_set_wake()
256 atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line)); in atmel_gpio_irq_set_wake()
274 return irq_find_mapping(atmel_pioctrl->irq_domain, offset); in atmel_gpio_to_irq()
283 int n, bank = -1; in atmel_gpio_irq_handler() local
285 /* Find from which bank is the irq received. */ in atmel_gpio_irq_handler()
286 for (n = 0; n < atmel_pioctrl->nbanks; n++) { in atmel_gpio_irq_handler()
287 if (atmel_pioctrl->irqs[n] == irq) { in atmel_gpio_irq_handler()
288 bank = n; in atmel_gpio_irq_handler()
293 if (bank < 0) { in atmel_gpio_irq_handler()
294 dev_err(atmel_pioctrl->dev, in atmel_gpio_irq_handler()
295 "no bank associated to irq %u\n", irq); in atmel_gpio_irq_handler()
302 isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, in atmel_gpio_irq_handler()
304 isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, in atmel_gpio_irq_handler()
311 atmel_pioctrl->gpio_chip, in atmel_gpio_irq_handler()
312 bank * ATMEL_PIO_NPINS_PER_BANK + n)); in atmel_gpio_irq_handler()
322 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; in atmel_gpio_direction_input()
325 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, in atmel_gpio_direction_input()
326 BIT(pin->line)); in atmel_gpio_direction_input()
327 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); in atmel_gpio_direction_input()
329 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); in atmel_gpio_direction_input()
337 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; in atmel_gpio_get()
340 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR); in atmel_gpio_get()
342 return !!(reg & BIT(pin->line)); in atmel_gpio_get()
349 unsigned int bank; in atmel_gpio_get_multiple() local
351 bitmap_zero(bits, atmel_pioctrl->npins); in atmel_gpio_get_multiple()
353 for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) { in atmel_gpio_get_multiple()
354 unsigned int word = bank; in atmel_gpio_get_multiple()
359 word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK); in atmel_gpio_get_multiple()
360 offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG; in atmel_gpio_get_multiple()
365 reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR); in atmel_gpio_get_multiple()
377 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; in atmel_gpio_direction_output()
380 atmel_gpio_write(atmel_pioctrl, pin->bank, in atmel_gpio_direction_output()
382 BIT(pin->line)); in atmel_gpio_direction_output()
384 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, in atmel_gpio_direction_output()
385 BIT(pin->line)); in atmel_gpio_direction_output()
386 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); in atmel_gpio_direction_output()
388 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); in atmel_gpio_direction_output()
396 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; in atmel_gpio_set()
398 atmel_gpio_write(atmel_pioctrl, pin->bank, in atmel_gpio_set()
400 BIT(pin->line)); in atmel_gpio_set()
407 unsigned int bank; in atmel_gpio_set_multiple() local
409 for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) { in atmel_gpio_set_multiple()
411 unsigned int word = bank; in atmel_gpio_set_multiple()
414 * On a 64-bit platform, BITS_PER_LONG is 64 so it is necessary to iterate over in atmel_gpio_set_multiple()
418 word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK); in atmel_gpio_set_multiple()
424 atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask); in atmel_gpio_set_multiple()
427 atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask); in atmel_gpio_set_multiple()
447 /* --- PINCTRL --- */
452 unsigned int bank = atmel_pioctrl->pins[pin_id]->bank; in atmel_pin_config_read() local
453 unsigned int line = atmel_pioctrl->pins[pin_id]->line; in atmel_pin_config_read()
454 void __iomem *addr = atmel_pioctrl->reg_base in atmel_pin_config_read()
455 + bank * ATMEL_PIO_BANK_OFFSET; in atmel_pin_config_read()
468 unsigned int bank = atmel_pioctrl->pins[pin_id]->bank; in atmel_pin_config_write() local
469 unsigned int line = atmel_pioctrl->pins[pin_id]->line; in atmel_pin_config_write()
470 void __iomem *addr = atmel_pioctrl->reg_base in atmel_pin_config_write()
471 + bank * ATMEL_PIO_BANK_OFFSET; in atmel_pin_config_write()
483 return atmel_pioctrl->npins; in atmel_pctl_get_groups_count()
491 return atmel_pioctrl->groups[selector].name; in atmel_pctl_get_group_name()
501 *pins = (unsigned int *)&atmel_pioctrl->groups[selector].pin; in atmel_pctl_get_group_pins()
513 for (i = 0; i < atmel_pioctrl->npins; i++) { in atmel_pctl_find_group_by_pin()
514 struct atmel_group *grp = atmel_pioctrl->groups + i; in atmel_pctl_find_group_by_pin()
516 if (grp->pin == pin) in atmel_pctl_find_group_by_pin()
536 return -EINVAL; in atmel_pctl_xlate_pinfunc()
542 return -EINVAL; in atmel_pctl_xlate_pinfunc()
543 *grp_name = grp->name; in atmel_pctl_xlate_pinfunc()
545 atmel_pioctrl->pins[pin_id]->mux = func_id; in atmel_pctl_xlate_pinfunc()
546 atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc); in atmel_pctl_xlate_pinfunc()
548 if (np->parent == atmel_pioctrl->node) in atmel_pctl_xlate_pinfunc()
549 atmel_pioctrl->pins[pin_id]->device = np->name; in atmel_pctl_xlate_pinfunc()
551 atmel_pioctrl->pins[pin_id]->device = np->parent->name; in atmel_pctl_xlate_pinfunc()
570 return -EINVAL; in atmel_pctl_dt_subnode_to_map()
575 dev_err(pctldev->dev, "%pOF: could not parse node property\n", in atmel_pctl_dt_subnode_to_map()
580 num_pins = pins->length / sizeof(u32); in atmel_pctl_dt_subnode_to_map()
582 dev_err(pctldev->dev, "no pins found in node %pOF\n", np); in atmel_pctl_dt_subnode_to_map()
583 ret = -EINVAL; in atmel_pctl_dt_subnode_to_map()
660 dev_err(pctldev->dev, "can't create maps for node %pOF\n", in atmel_pctl_dt_node_to_map()
693 *groups = atmel_pioctrl->group_names; in atmel_pmx_get_function_groups()
694 *num_groups = atmel_pioctrl->npins; in atmel_pmx_get_function_groups()
707 dev_dbg(pctldev->dev, "enable function %s group %s\n", in atmel_pmx_set_mux()
708 atmel_functions[function], atmel_pioctrl->groups[group].name); in atmel_pmx_set_mux()
710 pin = atmel_pioctrl->groups[group].pin; in atmel_pmx_set_mux()
714 dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf); in atmel_pmx_set_mux()
733 struct atmel_group *grp = atmel_pioctrl->groups + group; in atmel_conf_pin_config_group_get()
734 unsigned int pin_id = grp->pin; in atmel_conf_pin_config_group_get()
742 return -EINVAL; in atmel_conf_pin_config_group_get()
748 return -EINVAL; in atmel_conf_pin_config_group_get()
754 return -EINVAL; in atmel_conf_pin_config_group_get()
759 return -EINVAL; in atmel_conf_pin_config_group_get()
764 return -EINVAL; in atmel_conf_pin_config_group_get()
769 return -EINVAL; in atmel_conf_pin_config_group_get()
773 if (!atmel_pioctrl->slew_rate_support) in atmel_conf_pin_config_group_get()
774 return -EOPNOTSUPP; in atmel_conf_pin_config_group_get()
776 return -EINVAL; in atmel_conf_pin_config_group_get()
781 return -EINVAL; in atmel_conf_pin_config_group_get()
785 return -ENOTSUPP; in atmel_conf_pin_config_group_get()
787 return -ENOTSUPP; in atmel_conf_pin_config_group_get()
800 struct atmel_group *grp = atmel_pioctrl->groups + group; in atmel_conf_pin_config_group_set()
801 unsigned int bank, pin, pin_id = grp->pin; in atmel_conf_pin_config_group_set() local
808 if (atmel_pioctrl->slew_rate_support) in atmel_conf_pin_config_group_set()
815 dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", in atmel_conf_pin_config_group_set()
850 * - can't have different debounce periods inside a same group, in atmel_conf_pin_config_group_set()
851 * - the register to configure this period is a secure register. in atmel_conf_pin_config_group_set()
861 bank = ATMEL_PIO_BANK(pin_id); in atmel_conf_pin_config_group_set()
866 writel_relaxed(mask, atmel_pioctrl->reg_base + in atmel_conf_pin_config_group_set()
867 bank * ATMEL_PIO_BANK_OFFSET + in atmel_conf_pin_config_group_set()
870 writel_relaxed(mask, atmel_pioctrl->reg_base + in atmel_conf_pin_config_group_set()
871 bank * ATMEL_PIO_BANK_OFFSET + in atmel_conf_pin_config_group_set()
876 if (!atmel_pioctrl->slew_rate_support) in atmel_conf_pin_config_group_set()
891 dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n"); in atmel_conf_pin_config_group_set()
895 return -ENOTSUPP; in atmel_conf_pin_config_group_set()
897 dev_warn(pctldev->dev, in atmel_conf_pin_config_group_set()
904 dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf); in atmel_conf_pin_config_group_set()
917 return atmel_conf_pin_config_group_set(pctldev, grp->pin, configs, num_configs); in atmel_conf_pin_config_set()
926 return atmel_conf_pin_config_group_get(pctldev, grp->pin, configs); in atmel_conf_pin_config_get()
936 if (!atmel_pioctrl->pins[pin_id]->device) in atmel_conf_pin_config_dbg_show()
940 atmel_pioctrl->pins[pin_id]->device, in atmel_conf_pin_config_dbg_show()
941 atmel_pioctrl->pins[pin_id]->ioset); in atmel_conf_pin_config_dbg_show()
945 seq_printf(s, "%s ", "pull-up"); in atmel_conf_pin_config_dbg_show()
947 seq_printf(s, "%s ", "pull-down"); in atmel_conf_pin_config_dbg_show()
951 seq_printf(s, "%s ", "open-drain"); in atmel_conf_pin_config_dbg_show()
953 seq_printf(s, "%s ", "push-pull"); in atmel_conf_pin_config_dbg_show()
956 if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK)) in atmel_conf_pin_config_dbg_show()
957 seq_printf(s, "%s ", "slew-rate"); in atmel_conf_pin_config_dbg_show()
961 seq_printf(s, "%s ", "medium-drive"); in atmel_conf_pin_config_dbg_show()
964 seq_printf(s, "%s ", "high-drive"); in atmel_conf_pin_config_dbg_show()
968 seq_printf(s, "%s ", "low-drive"); in atmel_conf_pin_config_dbg_show()
994 * For each bank, save IMR to restore it later and disable all GPIO in atmel_pctrl_suspend()
997 for (i = 0; i < atmel_pioctrl->nbanks; i++) { in atmel_pctrl_suspend()
998 atmel_pioctrl->pm_suspend_backup[i].imr = in atmel_pctrl_suspend()
1001 ~atmel_pioctrl->pm_wakeup_sources[i]); in atmel_pctrl_suspend()
1002 atmel_pioctrl->pm_suspend_backup[i].odsr = in atmel_pctrl_suspend()
1007 atmel_pioctrl->pm_suspend_backup[i].cfgr[j] = in atmel_pctrl_suspend()
1021 for (i = 0; i < atmel_pioctrl->nbanks; i++) { in atmel_pctrl_resume()
1023 atmel_pioctrl->pm_suspend_backup[i].imr); in atmel_pctrl_resume()
1025 atmel_pioctrl->pm_suspend_backup[i].odsr); in atmel_pctrl_resume()
1030 atmel_pioctrl->pm_suspend_backup[i].cfgr[j]); in atmel_pctrl_resume()
1042 * The number of banks can be different from a SoC to another one.
1058 .compatible = "atmel,sama5d2-pinctrl",
1061 .compatible = "microchip,sama7g5-pinctrl",
1077 struct device *dev = &pdev->dev; in atmel_pinctrl_probe()
1086 return -ENOMEM; in atmel_pinctrl_probe()
1087 atmel_pioctrl->dev = dev; in atmel_pinctrl_probe()
1088 atmel_pioctrl->node = dev->of_node; in atmel_pinctrl_probe()
1093 return dev_err_probe(dev, -ENODEV, "Invalid device data\n"); in atmel_pinctrl_probe()
1095 atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks; in atmel_pinctrl_probe()
1096 atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK; in atmel_pinctrl_probe()
1097 /* if last bank has limited number of pins, adjust accordingly */ in atmel_pinctrl_probe()
1098 if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) { in atmel_pinctrl_probe()
1099 atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK; in atmel_pinctrl_probe()
1100 atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count; in atmel_pinctrl_probe()
1102 atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support; in atmel_pinctrl_probe()
1104 atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0); in atmel_pinctrl_probe()
1105 if (IS_ERR(atmel_pioctrl->reg_base)) in atmel_pinctrl_probe()
1106 return PTR_ERR(atmel_pioctrl->reg_base); in atmel_pinctrl_probe()
1108 atmel_pioctrl->clk = devm_clk_get_enabled(dev, NULL); in atmel_pinctrl_probe()
1109 if (IS_ERR(atmel_pioctrl->clk)) in atmel_pinctrl_probe()
1110 return dev_err_probe(dev, PTR_ERR(atmel_pioctrl->clk), "failed to get clock\n"); in atmel_pinctrl_probe()
1112 atmel_pioctrl->pins = devm_kcalloc(dev, in atmel_pinctrl_probe()
1113 atmel_pioctrl->npins, in atmel_pinctrl_probe()
1114 sizeof(*atmel_pioctrl->pins), in atmel_pinctrl_probe()
1116 if (!atmel_pioctrl->pins) in atmel_pinctrl_probe()
1117 return -ENOMEM; in atmel_pinctrl_probe()
1119 pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc), in atmel_pinctrl_probe()
1122 return -ENOMEM; in atmel_pinctrl_probe()
1124 atmel_pinctrl_desc.npins = atmel_pioctrl->npins; in atmel_pinctrl_probe()
1130 atmel_pioctrl->npins, sizeof(*group_names), in atmel_pinctrl_probe()
1133 return -ENOMEM; in atmel_pinctrl_probe()
1134 atmel_pioctrl->group_names = group_names; in atmel_pinctrl_probe()
1136 atmel_pioctrl->groups = devm_kcalloc(&pdev->dev, in atmel_pinctrl_probe()
1137 atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups), in atmel_pinctrl_probe()
1139 if (!atmel_pioctrl->groups) in atmel_pinctrl_probe()
1140 return -ENOMEM; in atmel_pinctrl_probe()
1141 for (i = 0 ; i < atmel_pioctrl->npins; i++) { in atmel_pinctrl_probe()
1142 struct atmel_group *group = atmel_pioctrl->groups + i; in atmel_pinctrl_probe()
1143 unsigned int bank = ATMEL_PIO_BANK(i); in atmel_pinctrl_probe() local
1146 atmel_pioctrl->pins[i] = devm_kzalloc(dev, in atmel_pinctrl_probe()
1147 sizeof(**atmel_pioctrl->pins), GFP_KERNEL); in atmel_pinctrl_probe()
1148 if (!atmel_pioctrl->pins[i]) in atmel_pinctrl_probe()
1149 return -ENOMEM; in atmel_pinctrl_probe()
1151 atmel_pioctrl->pins[i]->pin_id = i; in atmel_pinctrl_probe()
1152 atmel_pioctrl->pins[i]->bank = bank; in atmel_pinctrl_probe()
1153 atmel_pioctrl->pins[i]->line = line; in atmel_pinctrl_probe()
1155 pin_desc[i].number = i; in atmel_pinctrl_probe()
1157 pin_desc[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "P%c%u", in atmel_pinctrl_probe()
1158 bank + 'A', line); in atmel_pinctrl_probe()
1160 return -ENOMEM; in atmel_pinctrl_probe()
1162 group->name = group_names[i] = pin_desc[i].name; in atmel_pinctrl_probe()
1163 group->pin = pin_desc[i].number; in atmel_pinctrl_probe()
1165 dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line); in atmel_pinctrl_probe()
1168 atmel_pioctrl->gpio_chip = &atmel_gpio_chip; in atmel_pinctrl_probe()
1169 atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins; in atmel_pinctrl_probe()
1170 atmel_pioctrl->gpio_chip->label = dev_name(dev); in atmel_pinctrl_probe()
1171 atmel_pioctrl->gpio_chip->parent = dev; in atmel_pinctrl_probe()
1172 atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names; in atmel_pinctrl_probe()
1173 atmel_pioctrl->gpio_chip->set_config = gpiochip_generic_config; in atmel_pinctrl_probe()
1175 atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev, in atmel_pinctrl_probe()
1176 atmel_pioctrl->nbanks, in atmel_pinctrl_probe()
1177 sizeof(*atmel_pioctrl->pm_wakeup_sources), in atmel_pinctrl_probe()
1179 if (!atmel_pioctrl->pm_wakeup_sources) in atmel_pinctrl_probe()
1180 return -ENOMEM; in atmel_pinctrl_probe()
1182 atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev, in atmel_pinctrl_probe()
1183 atmel_pioctrl->nbanks, in atmel_pinctrl_probe()
1184 sizeof(*atmel_pioctrl->pm_suspend_backup), in atmel_pinctrl_probe()
1186 if (!atmel_pioctrl->pm_suspend_backup) in atmel_pinctrl_probe()
1187 return -ENOMEM; in atmel_pinctrl_probe()
1189 atmel_pioctrl->irqs = devm_kcalloc(dev, in atmel_pinctrl_probe()
1190 atmel_pioctrl->nbanks, in atmel_pinctrl_probe()
1191 sizeof(*atmel_pioctrl->irqs), in atmel_pinctrl_probe()
1193 if (!atmel_pioctrl->irqs) in atmel_pinctrl_probe()
1194 return -ENOMEM; in atmel_pinctrl_probe()
1196 /* There is one controller but each bank has its own irq line. */ in atmel_pinctrl_probe()
1197 for (i = 0; i < atmel_pioctrl->nbanks; i++) { in atmel_pinctrl_probe()
1204 atmel_pioctrl->irqs[i] = ret; in atmel_pinctrl_probe()
1206 dev_dbg(dev, "bank %i: irq=%d\n", i, ret); in atmel_pinctrl_probe()
1209 atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node, in atmel_pinctrl_probe()
1210 atmel_pioctrl->gpio_chip->ngpio, in atmel_pinctrl_probe()
1212 if (!atmel_pioctrl->irq_domain) in atmel_pinctrl_probe()
1213 return dev_err_probe(dev, -ENODEV, "can't add the irq domain\n"); in atmel_pinctrl_probe()
1215 for (i = 0; i < atmel_pioctrl->npins; i++) { in atmel_pinctrl_probe()
1216 int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i); in atmel_pinctrl_probe()
1227 atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev, in atmel_pinctrl_probe()
1230 if (IS_ERR(atmel_pioctrl->pinctrl_dev)) { in atmel_pinctrl_probe()
1231 ret = PTR_ERR(atmel_pioctrl->pinctrl_dev); in atmel_pinctrl_probe()
1236 ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl); in atmel_pinctrl_probe()
1242 ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev), in atmel_pinctrl_probe()
1243 0, 0, atmel_pioctrl->gpio_chip->ngpio); in atmel_pinctrl_probe()
1249 dev_info(&pdev->dev, "atmel pinctrl initialized\n"); in atmel_pinctrl_probe()
1254 gpiochip_remove(atmel_pioctrl->gpio_chip); in atmel_pinctrl_probe()
1257 irq_domain_remove(atmel_pioctrl->irq_domain); in atmel_pinctrl_probe()
1264 .name = "pinctrl-at91-pio4",