Lines Matching +full:tx +full:- +full:pins
2 * Driver for the Axis ARTPEC-6 pin controller
18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
26 #define ARTPEC6_LAST_PIN 97 /* 97 pins in pinmux */
59 struct pinctrl_pin_desc *pins; member
69 const unsigned int *pins; member
80 /* pins */
215 .pins = cpuclkout_pins0,
221 .pins = udlclkout_pins0,
227 .pins = i2c1_pins0,
233 .pins = i2c2_pins0,
239 .pins = i2c3_pins0,
245 .pins = i2s0_pins0,
251 .pins = i2s1_pins0,
257 .pins = i2srefclk_pins0,
263 .pins = spi0_pins0,
269 .pins = spi1_pins0,
275 .pins = pciedebug_pins0,
280 .name = "uart0grp0", /* All pins. */
281 .pins = uart0_pins0,
286 .name = "uart0grp1", /* RX/TX and RTS/CTS */
287 .pins = uart0_pins1,
292 .name = "uart0grp2", /* Only RX/TX pins. */
293 .pins = uart0_pins1,
294 .num_pins = ARRAY_SIZE(uart0_pins1) - 2,
298 .name = "uart1grp0", /* RX/TX and RTS/CTS */
299 .pins = uart1_pins0,
304 .name = "uart1grp1", /* Only RX/TX pins. */
305 .pins = uart1_pins0,
311 .pins = uart2_pins0,
316 .name = "uart2grp1", /* RX/TX and RTS/CTS */
317 .pins = uart2_pins1,
322 .name = "uart2grp2", /* Only RX/TX */
323 .pins = uart2_pins1,
328 .name = "uart3grp0", /* RX/TX and CTS/RTS */
329 .pins = uart3_pins0,
334 .name = "uart3grp1", /* Only RX/TX */
335 .pins = uart3_pins0,
341 .pins = uart4_pins0,
346 .name = "uart5grp0", /* TX/RX and RTS/CTS */
347 .pins = uart5_pins0,
352 .name = "uart5grp1", /* Only TX/RX */
353 .pins = uart5_pins0,
358 .name = "uart5nocts", /* TX/RX/RTS */
359 .pins = uart5_pins0,
360 .num_pins = ARRAY_SIZE(uart5_pins0) - 1,
365 .pins = nand_pins0,
371 .pins = sdio0_pins0,
377 .pins = sdio1_pins0,
383 .pins = ethernet_pins0,
401 { 0, 35, 0x0 }, /* 0x0 - 0x8c */
402 { 36, 52, 0x100 }, /* 0x100 - 0x140 */
403 { 53, 96, 0x180 }, /* 0x180 - 0x22c */
412 return (pin - pin_register[i].start) * 4 + in artpec6_pmx_reg_offset()
437 const unsigned int **pins, in artpec6_get_group_pins() argument
440 *pins = (unsigned int *)artpec6_pin_groups[group].pins; in artpec6_get_group_pins()
457 return -EINVAL; in artpec6_pconf_drive_mA_to_field()
664 * Registers for pins above a ARTPEC6_MAX_MUXABLE in artpec6_pmx_select_func()
667 if (artpec6_pin_groups[group].pins[i] > ARTPEC6_MAX_MUXABLE) in artpec6_pmx_select_func()
682 reg = artpec6_pmx_reg_offset(artpec6_pin_groups[group].pins[i]); in artpec6_pmx_select_func()
684 regval = readl(pmx->base + reg); in artpec6_pmx_select_func()
687 writel(regval, pmx->base + reg); in artpec6_pmx_select_func()
697 dev_dbg(pmx->dev, "enabling %s function for pin group %s\n", in artpec6_pmx_set()
715 return -EINVAL; in artpec6_pmx_request_gpio()
717 val = readl_relaxed(pmx->base + reg); in artpec6_pmx_request_gpio()
720 writel_relaxed(val, pmx->base + reg); in artpec6_pmx_request_gpio()
741 if (pin >= pmx->num_pins) { in artpec6_pconf_get()
742 dev_dbg(pmx->dev, "pinconf is not supported for pin %s\n", in artpec6_pconf_get()
743 pmx->pins[pin].name); in artpec6_pconf_get()
744 return -ENOTSUPP; in artpec6_pconf_get()
747 dev_dbg(pmx->dev, "getting configuration for pin %s\n", in artpec6_pconf_get()
748 pmx->pins[pin].name); in artpec6_pconf_get()
751 regval = readl(pmx->base + artpec6_pmx_reg_offset(pin)); in artpec6_pconf_get()
757 return -EINVAL; in artpec6_pconf_get()
763 return -EINVAL; in artpec6_pconf_get()
768 return -EINVAL; in artpec6_pconf_get()
777 return -ENOTSUPP; in artpec6_pconf_get()
805 if (pin >= pmx->num_pins) { in artpec6_pconf_set()
806 dev_dbg(pmx->dev, "pinconf is not supported for pin %s\n", in artpec6_pconf_set()
807 pmx->pins[pin].name); in artpec6_pconf_set()
808 return -ENOTSUPP; in artpec6_pconf_set()
811 dev_dbg(pmx->dev, "setting configuration for pin %s\n", in artpec6_pconf_set()
812 pmx->pins[pin].name); in artpec6_pconf_set()
814 reg = pmx->base + artpec6_pmx_reg_offset(pin); in artpec6_pconf_set()
832 dev_dbg(pctldev->dev, "%s: arg %u out of range\n", in artpec6_pconf_set()
834 return -EINVAL; in artpec6_pconf_set()
845 dev_dbg(pctldev->dev, "%s: arg %u out of range\n", in artpec6_pconf_set()
847 return -EINVAL; in artpec6_pconf_set()
859 dev_dbg(pctldev->dev, "%s: arg %u out of range\n", in artpec6_pconf_set()
861 return -EINVAL; in artpec6_pconf_set()
871 dev_dbg(pmx->dev, "parameter not supported\n"); in artpec6_pconf_set()
872 return -ENOTSUPP; in artpec6_pconf_set()
886 dev_dbg(pctldev->dev, "setting group %s configuration\n", in artpec6_pconf_group_set()
893 artpec6_pin_groups[group].pins[current_pin], in artpec6_pconf_group_set()
911 .name = "artpec6-pinctrl",
913 .pins = artpec6_pins,
923 void __iomem *base = pmx->base; in artpec6_pmx_reset()
940 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); in artpec6_pmx_probe()
942 return -ENOMEM; in artpec6_pmx_probe()
944 pmx->dev = &pdev->dev; in artpec6_pmx_probe()
946 pmx->base = devm_platform_ioremap_resource(pdev, 0); in artpec6_pmx_probe()
948 if (IS_ERR(pmx->base)) in artpec6_pmx_probe()
949 return PTR_ERR(pmx->base); in artpec6_pmx_probe()
953 pmx->pins = artpec6_pins; in artpec6_pmx_probe()
954 pmx->num_pins = ARRAY_SIZE(artpec6_pins); in artpec6_pmx_probe()
955 pmx->functions = artpec6_pmx_functions; in artpec6_pmx_probe()
956 pmx->num_functions = ARRAY_SIZE(artpec6_pmx_functions); in artpec6_pmx_probe()
957 pmx->pin_groups = artpec6_pin_groups; in artpec6_pmx_probe()
958 pmx->num_pin_groups = ARRAY_SIZE(artpec6_pin_groups); in artpec6_pmx_probe()
959 pmx->pctl = pinctrl_register(&artpec6_desc, &pdev->dev, pmx); in artpec6_pmx_probe()
961 if (IS_ERR(pmx->pctl)) { in artpec6_pmx_probe()
962 dev_err(&pdev->dev, "could not register pinctrl driver\n"); in artpec6_pmx_probe()
963 return PTR_ERR(pmx->pctl); in artpec6_pmx_probe()
968 dev_info(&pdev->dev, "initialised Axis ARTPEC-6 pinctrl driver\n"); in artpec6_pmx_probe()
977 pinctrl_unregister(pmx->pctl); in artpec6_pmx_remove()
981 { .compatible = "axis,artpec6-pinctrl" },
987 .name = "artpec6-pinctrl",