pinctrl/mediatek/pinctrl-mt8173.c

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (c) 2014-2015 MediaTek Inc.
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
15 #include "pinctrl-mtk-common.h"
16 #include "pinctrl-mtk-mt8173.h"
21 	MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0),  /* KROW0 */
23 	MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
24 	MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0),  /* KCOL0 */
26 	MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
28 	MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0),   /* ms0 DS */
29 	MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0),   /* ms0 RST */
30 	MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0),   /* ms0 cmd */
31 	MTK_PIN_PUPD_SPEC_SR(65, 0xc00, 2, 1, 0),   /* ms0 clk */
32 	MTK_PIN_PUPD_SPEC_SR(57, 0xc20, 2, 1, 0),   /* ms0 data0 */
33 	MTK_PIN_PUPD_SPEC_SR(58, 0xc20, 2, 1, 0),   /* ms0 data1 */
34 	MTK_PIN_PUPD_SPEC_SR(59, 0xc20, 2, 1, 0),   /* ms0 data2 */
35 	MTK_PIN_PUPD_SPEC_SR(60, 0xc20, 2, 1, 0),   /* ms0 data3 */
36 	MTK_PIN_PUPD_SPEC_SR(61, 0xc20, 2, 1, 0),   /* ms0 data4 */
37 	MTK_PIN_PUPD_SPEC_SR(62, 0xc20, 2, 1, 0),   /* ms0 data5 */
38 	MTK_PIN_PUPD_SPEC_SR(63, 0xc20, 2, 1, 0),   /* ms0 data6 */
39 	MTK_PIN_PUPD_SPEC_SR(64, 0xc20, 2, 1, 0),   /* ms0 data7 */
41 	MTK_PIN_PUPD_SPEC_SR(78, 0xc50, 2, 1, 0),    /* ms1 cmd */
42 	MTK_PIN_PUPD_SPEC_SR(73, 0xd20, 2, 1, 0),    /* ms1 dat0 */
44 	MTK_PIN_PUPD_SPEC_SR(75, 0xd20, 10, 9, 8),   /* ms1 dat2 */
46 	MTK_PIN_PUPD_SPEC_SR(77, 0xc40, 2, 1, 0),    /* ms1 clk */
48 	MTK_PIN_PUPD_SPEC_SR(100, 0xd40, 2, 1, 0),    /* ms2 dat0 */
50 	MTK_PIN_PUPD_SPEC_SR(102, 0xd40, 10, 9, 8),   /* ms2 dat2 */
52 	MTK_PIN_PUPD_SPEC_SR(104, 0xc80, 2, 1, 0),    /* ms2 clk */
53 	MTK_PIN_PUPD_SPEC_SR(105, 0xc90, 2, 1, 0),    /* ms2 cmd */
55 	MTK_PIN_PUPD_SPEC_SR(22, 0xd60, 2, 1, 0),    /* ms3 dat0 */
57 	MTK_PIN_PUPD_SPEC_SR(24, 0xd60, 10, 9, 8),   /* ms3 dat2 */
59 	MTK_PIN_PUPD_SPEC_SR(26, 0xcc0, 2, 1, 0),    /* ms3 clk */
60 	MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0)     /* ms3 cmd */
65 	MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2),
69 	MTK_PIN_IES_SMT_SPEC(17, 17, 0x950, 2),
96 	MTK_PIN_IES_SMT_SPEC(86, 91, 0x950, 2),
105 	MTK_PIN_IES_SMT_SPEC(113, 116, 0x940, 2),
110 	MTK_PIN_IES_SMT_SPEC(128, 128, 0x950, 8),
112 	MTK_PIN_IES_SMT_SPEC(131, 132, 0x950, 8),
113 	MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
118 	MTK_PIN_IES_SMT_SPEC(5, 9, 0x900, 2),
122 	MTK_PIN_IES_SMT_SPEC(17, 17, 0x920, 2),
149 	MTK_PIN_IES_SMT_SPEC(86, 91, 0x920, 2),
158 	MTK_PIN_IES_SMT_SPEC(113, 116, 0x910, 2),
163 	MTK_PIN_IES_SMT_SPEC(128, 128, 0x920, 8),
165 	MTK_PIN_IES_SMT_SPEC(131, 132, 0x920, 8),
166 	MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
170 	/* 0E4E8SR 4/8/12/16 */
171 	MTK_DRV_GRP(4, 16, 1, 2, 4),
172 	/* 0E2E4SR  2/4/6/8 */
173 	MTK_DRV_GRP(2, 8, 1, 2, 2),
174 	/* E8E4E2  2/4/6/8/10/12/14/16 */
175 	MTK_DRV_GRP(2, 16, 0, 2, 2)
181 	MTK_PIN_DRV_GRP(2, DRV_BASE+0x20, 12, 0),
187 	MTK_PIN_DRV_GRP(8, DRV_BASE+0x30, 0, 0),
193 	MTK_PIN_DRV_GRP(14, DRV_BASE+0x40, 8, 1),
194 	MTK_PIN_DRV_GRP(15, DRV_BASE+0x40, 8, 1),
195 	MTK_PIN_DRV_GRP(16, DRV_BASE, 8, 1),
196 	MTK_PIN_DRV_GRP(17, 0xce0, 8, 2),
197 	MTK_PIN_DRV_GRP(22, 0xce0, 8, 2),
198 	MTK_PIN_DRV_GRP(23, 0xce0, 8, 2),
199 	MTK_PIN_DRV_GRP(24, 0xce0, 8, 2),
200 	MTK_PIN_DRV_GRP(25, 0xce0, 8, 2),
201 	MTK_PIN_DRV_GRP(26, 0xcc0, 8, 2),
202 	MTK_PIN_DRV_GRP(27, 0xcd0, 8, 2),
203 	MTK_PIN_DRV_GRP(28, 0xd70, 8, 2),
209 	MTK_PIN_DRV_GRP(34, DRV_BASE+0x10, 8, 1),
210 	MTK_PIN_DRV_GRP(35, DRV_BASE+0x10, 8, 1),
211 	MTK_PIN_DRV_GRP(36, DRV_BASE+0x10, 8, 1),
215 	MTK_PIN_DRV_GRP(40, DRV_BASE+0x20, 8, 0),
216 	MTK_PIN_DRV_GRP(41, DRV_BASE+0x20, 8, 0),
217 	MTK_PIN_DRV_GRP(42, DRV_BASE+0x50, 8, 1),
218 	MTK_PIN_DRV_GRP(57, 0xc20, 8, 2),
219 	MTK_PIN_DRV_GRP(58, 0xc20, 8, 2),
220 	MTK_PIN_DRV_GRP(59, 0xc20, 8, 2),
221 	MTK_PIN_DRV_GRP(60, 0xc20, 8, 2),
222 	MTK_PIN_DRV_GRP(61, 0xc20, 8, 2),
223 	MTK_PIN_DRV_GRP(62, 0xc20, 8, 2),
224 	MTK_PIN_DRV_GRP(63, 0xc20, 8, 2),
225 	MTK_PIN_DRV_GRP(64, 0xc20, 8, 2),
226 	MTK_PIN_DRV_GRP(65, 0xc00, 8, 2),
227 	MTK_PIN_DRV_GRP(66, 0xc10, 8, 2),
228 	MTK_PIN_DRV_GRP(67, 0xd10, 8, 2),
229 	MTK_PIN_DRV_GRP(68, 0xd00, 8, 2),
234 	MTK_PIN_DRV_GRP(73, 0xc60, 8, 2),
235 	MTK_PIN_DRV_GRP(74, 0xc60, 8, 2),
236 	MTK_PIN_DRV_GRP(75, 0xc60, 8, 2),
237 	MTK_PIN_DRV_GRP(76, 0xc60, 8, 2),
238 	MTK_PIN_DRV_GRP(77, 0xc40, 8, 2),
239 	MTK_PIN_DRV_GRP(78, 0xc50, 8, 2),
247 	MTK_PIN_DRV_GRP(85, DRV_BASE+0x60, 8, 1),
248 	MTK_PIN_DRV_GRP(86, DRV_BASE+0x60, 8, 1),
249 	MTK_PIN_DRV_GRP(87, DRV_BASE+0x60, 8, 1),
250 	MTK_PIN_DRV_GRP(88, DRV_BASE+0x60, 8, 1),
251 	MTK_PIN_DRV_GRP(89, DRV_BASE+0x60, 8, 1),
252 	MTK_PIN_DRV_GRP(90, DRV_BASE+0x60, 8, 1),
253 	MTK_PIN_DRV_GRP(91, DRV_BASE+0x60, 8, 1),
258 	MTK_PIN_DRV_GRP(96, DRV_BASE+0x80, 8, 1),
259 	MTK_PIN_DRV_GRP(97, DRV_BASE+0x80, 8, 1),
260 	MTK_PIN_DRV_GRP(98, DRV_BASE+0x80, 8, 1),
261 	MTK_PIN_DRV_GRP(99, DRV_BASE+0x80, 8, 1),
262 	MTK_PIN_DRV_GRP(100, 0xca0, 8, 2),
263 	MTK_PIN_DRV_GRP(101, 0xca0, 8, 2),
264 	MTK_PIN_DRV_GRP(102, 0xca0, 8, 2),
265 	MTK_PIN_DRV_GRP(103, 0xca0, 8, 2),
266 	MTK_PIN_DRV_GRP(104, 0xc80, 8, 2),
267 	MTK_PIN_DRV_GRP(105, 0xc90, 8, 2),
287 	MTK_PIN_DRV_GRP(127, DRV_BASE+0x50, 8, 1),
340 		.compatible = "mediatek,mt8173-pinctrl",
348 		.name = "mediatek-mt8173-pinctrl",