pinctrl/mediatek/pinctrl-mt2712.c

1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/pinctrl/pinconf-generic.h>
14 #include <dt-bindings/pinctrl/mt65xx.h>
16 #include "pinctrl-mtk-common.h"
17 #include "pinctrl-mtk-mt2712.h"
20 	MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
24 	MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
25 	MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
27 	MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
29 	MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
31 	MTK_PIN_PUPD_SPEC_SR(34, 0xf40, 2, 1, 0),
33 	MTK_PIN_PUPD_SPEC_SR(36, 0xf40, 10, 9, 8),
34 	MTK_PIN_PUPD_SPEC_SR(37, 0xc40, 2, 1, 0),
35 	MTK_PIN_PUPD_SPEC_SR(38, 0xc60, 2, 1, 0),
36 	MTK_PIN_PUPD_SPEC_SR(39, 0xc60, 2, 1, 0),
37 	MTK_PIN_PUPD_SPEC_SR(40, 0xc60, 2, 1, 0),
38 	MTK_PIN_PUPD_SPEC_SR(41, 0xc60, 2, 1, 0),
39 	MTK_PIN_PUPD_SPEC_SR(42, 0xc60, 2, 1, 0),
40 	MTK_PIN_PUPD_SPEC_SR(43, 0xc60, 2, 1, 0),
41 	MTK_PIN_PUPD_SPEC_SR(44, 0xc60, 2, 1, 0),
42 	MTK_PIN_PUPD_SPEC_SR(45, 0xc60, 2, 1, 0),
43 	MTK_PIN_PUPD_SPEC_SR(46, 0xc50, 2, 1, 0),
44 	MTK_PIN_PUPD_SPEC_SR(47, 0xda0, 2, 1, 0),
45 	MTK_PIN_PUPD_SPEC_SR(48, 0xd90, 2, 1, 0),
47 	MTK_PIN_PUPD_SPEC_SR(50, 0xdf0, 10, 9, 8),
49 	MTK_PIN_PUPD_SPEC_SR(52, 0xdf0, 2, 1, 0),
50 	MTK_PIN_PUPD_SPEC_SR(53, 0xd50, 2, 1, 0),
51 	MTK_PIN_PUPD_SPEC_SR(54, 0xd80, 2, 1, 0),
52 	MTK_PIN_PUPD_SPEC_SR(55, 0xe00, 2, 1, 0),
53 	MTK_PIN_PUPD_SPEC_SR(56, 0xd40, 2, 1, 0),
55 	MTK_PIN_PUPD_SPEC_SR(63, 0xc80, 2, 1, 0),
58 	MTK_PIN_PUPD_SPEC_SR(66, 0xdb0, 10, 9, 8),
59 	MTK_PIN_PUPD_SPEC_SR(67, 0xcd0, 2, 1, 0),
60 	MTK_PIN_PUPD_SPEC_SR(68, 0xdb0, 2, 1, 0),
61 	MTK_PIN_PUPD_SPEC_SR(69, 0xc90, 2, 1, 0),
62 	MTK_PIN_PUPD_SPEC_SR(70, 0xcc0, 2, 1, 0),
64 	MTK_PIN_PUPD_SPEC_SR(89, 0xce0, 2, 1, 0),
66 	MTK_PIN_PUPD_SPEC_SR(91, 0xdd0, 10, 9, 8),
68 	MTK_PIN_PUPD_SPEC_SR(93, 0xdd0, 2, 1, 0),
69 	MTK_PIN_PUPD_SPEC_SR(94, 0xd20, 2, 1, 0),
70 	MTK_PIN_PUPD_SPEC_SR(95, 0xcf0, 2, 1, 0),
71 	MTK_PIN_PUPD_SPEC_SR(96, 0xd30, 2, 1, 0),
76 	MTK_PIN_PUPD_SPEC_SR(138, 0xe70, 8, 7, 6),
79 	MTK_PIN_PUPD_SPEC_SR(141, 0xe60, 2, 1, 0),
84 	MTK_PIN_IES_SMT_SPEC(0, 3, 0x900, 2),
86 	MTK_PIN_IES_SMT_SPEC(8, 11, 0x900, 1),
92 	MTK_PIN_IES_SMT_SPEC(24, 25, 0x8d0, 2),
114 	MTK_PIN_IES_SMT_SPEC(71, 74, 0x8d0, 8),
129 	MTK_PIN_IES_SMT_SPEC(110, 110, 0x8e0, 2),
135 	MTK_PIN_IES_SMT_SPEC(116, 116, 0x8e0, 2),
144 	MTK_PIN_IES_SMT_SPEC(131, 134, 0x8e0, 8),
155 	MTK_PIN_IES_SMT_SPEC(174, 175, 0x8f0, 2),
166 	MTK_PIN_IES_SMT_SPEC(187, 187, 0x8f0, 8),
168 	MTK_PIN_IES_SMT_SPEC(189, 189, 0x8f0, 8),
181 	MTK_PIN_IES_SMT_SPEC(0, 3, 0x8c0, 2),
183 	MTK_PIN_IES_SMT_SPEC(8, 9, 0x8c0, 1),
190 	MTK_PIN_IES_SMT_SPEC(24, 25, 0x890, 2),
211 	MTK_PIN_IES_SMT_SPEC(71, 74, 0x890, 8),
226 	MTK_PIN_IES_SMT_SPEC(110, 110, 0x8a0, 2),
232 	MTK_PIN_IES_SMT_SPEC(116, 116, 0x8a0, 2),
241 	MTK_PIN_IES_SMT_SPEC(131, 135, 0x8a0, 8),
252 	MTK_PIN_IES_SMT_SPEC(174, 175, 0x8b0, 2),
263 	MTK_PIN_IES_SMT_SPEC(187, 187, 0x8b0, 8),
265 	MTK_PIN_IES_SMT_SPEC(189, 189, 0x8b0, 8),
278 	/* 0E4E8SR 4/8/12/16 */
279 	MTK_DRV_GRP(4, 16, 1, 2, 4),
280 	/* 0E2E4SR  2/4/6/8 */
281 	MTK_DRV_GRP(2, 8, 1, 2, 2),
282 	/* E8E4E2  2/4/6/8/10/12/14/16 */
283 	MTK_DRV_GRP(2, 16, 0, 2, 2)
289 	MTK_PIN_DRV_GRP(2, 0xc10, 4, 0),
297 	MTK_PIN_DRV_GRP(8, 0xc10, 0, 0),
319 	MTK_PIN_DRV_GRP(25, 0xb40, 8, 0),
328 	MTK_PIN_DRV_GRP(30, 0xf50, 8, 2),
329 	MTK_PIN_DRV_GRP(31, 0xf50, 8, 2),
330 	MTK_PIN_DRV_GRP(32, 0xf50, 8, 2),
331 	MTK_PIN_DRV_GRP(33, 0xf50, 8, 2),
332 	MTK_PIN_DRV_GRP(34, 0xf50, 8, 2),
333 	MTK_PIN_DRV_GRP(35, 0xf50, 8, 2),
334 	MTK_PIN_DRV_GRP(36, 0xf50, 8, 2),
336 	MTK_PIN_DRV_GRP(37, 0xc40, 8, 2),
338 	MTK_PIN_DRV_GRP(38, 0xc60, 8, 2),
339 	MTK_PIN_DRV_GRP(39, 0xc60, 8, 2),
340 	MTK_PIN_DRV_GRP(40, 0xc60, 8, 2),
341 	MTK_PIN_DRV_GRP(41, 0xc60, 8, 2),
342 	MTK_PIN_DRV_GRP(42, 0xc60, 8, 2),
343 	MTK_PIN_DRV_GRP(43, 0xc60, 8, 2),
344 	MTK_PIN_DRV_GRP(44, 0xc60, 8, 2),
345 	MTK_PIN_DRV_GRP(45, 0xc60, 8, 2),
347 	MTK_PIN_DRV_GRP(46, 0xc50, 8, 2),
349 	MTK_PIN_DRV_GRP(47, 0xda0, 8, 2),
351 	MTK_PIN_DRV_GRP(48, 0xd90, 8, 2),
353 	MTK_PIN_DRV_GRP(49, 0xd60, 8, 2),
354 	MTK_PIN_DRV_GRP(50, 0xd60, 8, 2),
355 	MTK_PIN_DRV_GRP(51, 0xd60, 8, 2),
356 	MTK_PIN_DRV_GRP(52, 0xd60, 8, 2),
358 	MTK_PIN_DRV_GRP(53, 0xd50, 8, 2),
360 	MTK_PIN_DRV_GRP(54, 0xd80, 8, 2),
362 	MTK_PIN_DRV_GRP(55, 0xe00, 8, 2),
364 	MTK_PIN_DRV_GRP(56, 0xd40, 8, 2),
366 	MTK_PIN_DRV_GRP(63, 0xc80, 8, 2),
368 	MTK_PIN_DRV_GRP(64, 0xca0, 8, 2),
369 	MTK_PIN_DRV_GRP(65, 0xca0, 8, 2),
370 	MTK_PIN_DRV_GRP(66, 0xca0, 8, 2),
372 	MTK_PIN_DRV_GRP(67, 0xcd0, 8, 2),
374 	MTK_PIN_DRV_GRP(68, 0xca0, 8, 2),
376 	MTK_PIN_DRV_GRP(69, 0xc90, 8, 2),
378 	MTK_PIN_DRV_GRP(70, 0xcc0, 8, 2),
380 	MTK_PIN_DRV_GRP(71, 0xb60, 8, 1),
381 	MTK_PIN_DRV_GRP(72, 0xb60, 8, 1),
382 	MTK_PIN_DRV_GRP(73, 0xb60, 8, 1),
383 	MTK_PIN_DRV_GRP(74, 0xb60, 8, 1),
402 	MTK_PIN_DRV_GRP(89, 0xce0, 8, 2),
404 	MTK_PIN_DRV_GRP(90, 0xd00, 8, 2),
405 	MTK_PIN_DRV_GRP(91, 0xd00, 8, 2),
406 	MTK_PIN_DRV_GRP(92, 0xd00, 8, 2),
407 	MTK_PIN_DRV_GRP(93, 0xd00, 8, 2),
409 	MTK_PIN_DRV_GRP(94, 0xd20, 8, 2),
411 	MTK_PIN_DRV_GRP(95, 0xcf0, 8, 2),
413 	MTK_PIN_DRV_GRP(96, 0xd30, 8, 2),
420 	MTK_PIN_DRV_GRP(101, 0xb70, 8, 0),
421 	MTK_PIN_DRV_GRP(102, 0xb70, 8, 0),
422 	MTK_PIN_DRV_GRP(103, 0xb70, 8, 0),
423 	MTK_PIN_DRV_GRP(104, 0xb70, 8, 0),
451 	MTK_PIN_DRV_GRP(157, 0xbb0, 8, 0),
452 	MTK_PIN_DRV_GRP(158, 0xbb0, 8, 0),
453 	MTK_PIN_DRV_GRP(159, 0xbb0, 8, 0),
454 	MTK_PIN_DRV_GRP(160, 0xbb0, 8, 0),
469 	MTK_PIN_DRV_GRP(171, 0xbc0, 8, 0),
470 	MTK_PIN_DRV_GRP(172, 0xbc0, 8, 0),
481 	MTK_PIN_DRV_GRP(178, 0xbd0, 8, 0),
485 	MTK_PIN_DRV_GRP(180, 0xbd0, 8, 0),
497 	MTK_PIN_DRV_GRP(186, 0xbe0, 8, 0),
509 	MTK_PIN_DRV_GRP(192, 0xbf0, 8, 0),
514 	MTK_PIN_DRV_GRP(195, 0xbf0, 8, 0),
530 	MTK_PIN_DRV_GRP(207, 0xc00, 8, 0),
531 	MTK_PIN_DRV_GRP(208, 0xc00, 8, 0),
532 	MTK_PIN_DRV_GRP(209, 0xc00, 8, 0),
566 		.ports     = 8,
574 	{ .compatible = "mediatek,mt2712-pinctrl", .data = &mt2712_pinctrl_data },
582 		.name = "mediatek-mt2712-pinctrl",