Lines Matching +full:bit +full:- +full:per +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0+
8 // Based on pinctrl-imx.c:
29 #include "pinctrl-imx1.h"
56 #define MX1_MUX_FUNCTION(val) (BIT(0) & val)
57 #define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
58 #define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
59 #define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
60 #define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
61 #define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
69 * Those controls that are represented by 1 bit have a direct mapping between
70 * bit position and pin id. If they are represented by 2 bit, the lower 16 pins
72 * register. pin_id is stored in bit (pin_id%16)*2 and the bit above.
81 return ipctl->base + port * MX1_PORT_STRIDE; in imx1_mem()
85 * Write to a register with 2 bits per pin. The function will automatically
101 dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n", in imx1_write_2bit()
108 new_val = value & 0x3; /* Make sure value is really 2 bit */ in imx1_write_2bit()
128 new_val = value & 0x1; /* Make sure value is really 1 bit */ in imx1_write_bit()
145 return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset; in imx1_read_2bit()
154 return !!(readl(reg) & BIT(offset)); in imx1_read_bit()
164 for (i = 0; i < info->ngroups; i++) { in imx1_pinctrl_find_group_by_name()
165 if (!strcmp(info->groups[i].name, name)) { in imx1_pinctrl_find_group_by_name()
166 grp = &info->groups[i]; in imx1_pinctrl_find_group_by_name()
177 const struct imx1_pinctrl_soc_info *info = ipctl->info; in imx1_get_groups_count()
179 return info->ngroups; in imx1_get_groups_count()
186 const struct imx1_pinctrl_soc_info *info = ipctl->info; in imx1_get_group_name()
188 return info->groups[selector].name; in imx1_get_group_name()
196 const struct imx1_pinctrl_soc_info *info = ipctl->info; in imx1_get_group_pins()
198 if (selector >= info->ngroups) in imx1_get_group_pins()
199 return -EINVAL; in imx1_get_group_pins()
201 *pins = info->groups[selector].pin_ids; in imx1_get_group_pins()
202 *npins = info->groups[selector].npins; in imx1_get_group_pins()
226 const struct imx1_pinctrl_soc_info *info = ipctl->info; in imx1_dt_node_to_map()
237 grp = imx1_pinctrl_find_group_by_name(info, np->name); in imx1_dt_node_to_map()
239 dev_err(info->dev, "unable to find group for node %pOFn\n", in imx1_dt_node_to_map()
241 return -EINVAL; in imx1_dt_node_to_map()
244 for (i = 0; i < grp->npins; i++) in imx1_dt_node_to_map()
250 return -ENOMEM; in imx1_dt_node_to_map()
255 /* create mux map */ in imx1_dt_node_to_map()
259 return -EINVAL; in imx1_dt_node_to_map()
262 new_map[0].data.mux.function = parent->name; in imx1_dt_node_to_map()
263 new_map[0].data.mux.group = np->name; in imx1_dt_node_to_map()
268 for (i = j = 0; i < grp->npins; i++) { in imx1_dt_node_to_map()
271 pin_get_name(pctldev, grp->pins[i].pin_id); in imx1_dt_node_to_map()
272 new_map[j].data.configs.configs = &grp->pins[i].config; in imx1_dt_node_to_map()
277 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", in imx1_dt_node_to_map()
278 (*map)->data.mux.function, (*map)->data.mux.group, map_num); in imx1_dt_node_to_map()
302 const struct imx1_pinctrl_soc_info *info = ipctl->info; in imx1_pmx_set()
308 * Configure the mux mode for each pin in the group for a specific in imx1_pmx_set()
311 pins = info->groups[group].pins; in imx1_pmx_set()
312 npins = info->groups[group].npins; in imx1_pmx_set()
316 dev_dbg(ipctl->dev, "enable function %s group %s\n", in imx1_pmx_set()
317 info->functions[selector].name, info->groups[group].name); in imx1_pmx_set()
320 unsigned int mux = pins[i].mux_id; in imx1_pmx_set() local
322 unsigned int afunction = MX1_MUX_FUNCTION(mux); in imx1_pmx_set()
323 unsigned int gpio_in_use = MX1_MUX_GPIO(mux); in imx1_pmx_set()
324 unsigned int direction = MX1_MUX_DIR(mux); in imx1_pmx_set()
325 unsigned int gpio_oconf = MX1_MUX_OCONF(mux); in imx1_pmx_set()
326 unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux); in imx1_pmx_set()
327 unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux); in imx1_pmx_set()
329 …dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, icon… in imx1_pmx_set()
354 const struct imx1_pinctrl_soc_info *info = ipctl->info; in imx1_pmx_get_funcs_count()
356 return info->nfunctions; in imx1_pmx_get_funcs_count()
363 const struct imx1_pinctrl_soc_info *info = ipctl->info; in imx1_pmx_get_func_name()
365 return info->functions[selector].name; in imx1_pmx_get_func_name()
373 const struct imx1_pinctrl_soc_info *info = ipctl->info; in imx1_pmx_get_groups()
375 *groups = info->functions[selector].groups; in imx1_pmx_get_groups()
376 *num_groups = info->functions[selector].num_groups; in imx1_pmx_get_groups()
408 dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n", in imx1_pinconf_set()
409 pin_desc_get(pctldev, pin_id)->name); in imx1_pinconf_set()
428 const struct imx1_pinctrl_soc_info *info = ipctl->info; in imx1_pinconf_group_dbg_show()
434 if (group >= info->ngroups) in imx1_pinconf_group_dbg_show()
438 grp = &info->groups[group]; in imx1_pinconf_group_dbg_show()
439 for (i = 0; i < grp->npins; i++) { in imx1_pinconf_group_dbg_show()
440 name = pin_get_name(pctldev, grp->pins[i].pin_id); in imx1_pinconf_group_dbg_show()
441 ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config); in imx1_pinconf_group_dbg_show()
471 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); in imx1_pinctrl_parse_groups()
474 grp->name = np->name; in imx1_pinctrl_parse_groups()
482 dev_notice(info->dev, "Not a valid fsl,pins property (%pOFn)\n", in imx1_pinctrl_parse_groups()
484 return -EINVAL; in imx1_pinctrl_parse_groups()
487 grp->npins = size / 12; in imx1_pinctrl_parse_groups()
488 grp->pins = devm_kcalloc(info->dev, in imx1_pinctrl_parse_groups()
489 grp->npins, sizeof(struct imx1_pin), GFP_KERNEL); in imx1_pinctrl_parse_groups()
490 grp->pin_ids = devm_kcalloc(info->dev, in imx1_pinctrl_parse_groups()
491 grp->npins, sizeof(unsigned int), GFP_KERNEL); in imx1_pinctrl_parse_groups()
493 if (!grp->pins || !grp->pin_ids) in imx1_pinctrl_parse_groups()
494 return -ENOMEM; in imx1_pinctrl_parse_groups()
496 for (i = 0; i < grp->npins; i++) { in imx1_pinctrl_parse_groups()
497 grp->pins[i].pin_id = be32_to_cpu(*list++); in imx1_pinctrl_parse_groups()
498 grp->pins[i].mux_id = be32_to_cpu(*list++); in imx1_pinctrl_parse_groups()
499 grp->pins[i].config = be32_to_cpu(*list++); in imx1_pinctrl_parse_groups()
501 grp->pin_ids[i] = grp->pins[i].pin_id; in imx1_pinctrl_parse_groups()
517 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); in imx1_pinctrl_parse_functions()
519 func = &info->functions[index]; in imx1_pinctrl_parse_functions()
522 func->name = np->name; in imx1_pinctrl_parse_functions()
523 func->num_groups = of_get_child_count(np); in imx1_pinctrl_parse_functions()
524 if (func->num_groups == 0) in imx1_pinctrl_parse_functions()
525 return -EINVAL; in imx1_pinctrl_parse_functions()
527 func->groups = devm_kcalloc(info->dev, in imx1_pinctrl_parse_functions()
528 func->num_groups, sizeof(char *), GFP_KERNEL); in imx1_pinctrl_parse_functions()
530 if (!func->groups) in imx1_pinctrl_parse_functions()
531 return -ENOMEM; in imx1_pinctrl_parse_functions()
534 func->groups[i] = child->name; in imx1_pinctrl_parse_functions()
535 grp = &info->groups[grp_index++]; in imx1_pinctrl_parse_functions()
537 if (ret == -ENOMEM) in imx1_pinctrl_parse_functions()
547 struct device_node *np = pdev->dev.of_node; in imx1_pinctrl_parse_dt()
554 return -ENODEV; in imx1_pinctrl_parse_dt()
562 dev_err(&pdev->dev, "No pin functions defined\n"); in imx1_pinctrl_parse_dt()
563 return -EINVAL; in imx1_pinctrl_parse_dt()
566 info->nfunctions = nfuncs; in imx1_pinctrl_parse_dt()
567 info->functions = devm_kcalloc(&pdev->dev, in imx1_pinctrl_parse_dt()
570 info->ngroups = ngroups; in imx1_pinctrl_parse_dt()
571 info->groups = devm_kcalloc(&pdev->dev, in imx1_pinctrl_parse_dt()
575 if (!info->functions || !info->groups) in imx1_pinctrl_parse_dt()
576 return -ENOMEM; in imx1_pinctrl_parse_dt()
580 if (ret == -ENOMEM) in imx1_pinctrl_parse_dt()
581 return -ENOMEM; in imx1_pinctrl_parse_dt()
595 if (!info || !info->pins || !info->npins) { in imx1_pinctrl_core_probe()
596 dev_err(&pdev->dev, "wrong pinctrl info\n"); in imx1_pinctrl_core_probe()
597 return -EINVAL; in imx1_pinctrl_core_probe()
599 info->dev = &pdev->dev; in imx1_pinctrl_core_probe()
602 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); in imx1_pinctrl_core_probe()
604 return -ENOMEM; in imx1_pinctrl_core_probe()
608 return -ENOENT; in imx1_pinctrl_core_probe()
610 ipctl->base = devm_ioremap(&pdev->dev, res->start, in imx1_pinctrl_core_probe()
612 if (!ipctl->base) in imx1_pinctrl_core_probe()
613 return -ENOMEM; in imx1_pinctrl_core_probe()
616 pctl_desc->name = dev_name(&pdev->dev); in imx1_pinctrl_core_probe()
617 pctl_desc->pins = info->pins; in imx1_pinctrl_core_probe()
618 pctl_desc->npins = info->npins; in imx1_pinctrl_core_probe()
622 dev_err(&pdev->dev, "fail to probe dt properties\n"); in imx1_pinctrl_core_probe()
626 ipctl->info = info; in imx1_pinctrl_core_probe()
627 ipctl->dev = info->dev; in imx1_pinctrl_core_probe()
629 ipctl->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, ipctl); in imx1_pinctrl_core_probe()
630 if (IS_ERR(ipctl->pctl)) { in imx1_pinctrl_core_probe()
631 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); in imx1_pinctrl_core_probe()
632 return PTR_ERR(ipctl->pctl); in imx1_pinctrl_core_probe()
635 ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); in imx1_pinctrl_core_probe()
637 dev_err(&pdev->dev, "Failed to populate subdevices\n"); in imx1_pinctrl_core_probe()
641 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); in imx1_pinctrl_core_probe()