1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <linux/pinctrl/pinconf-generic.h>
17 #include <linux/pinctrl/pinconf.h>
18 #include <linux/pinctrl/pinctrl.h>
19 #include <linux/pinctrl/pinmux.h>
22 #include "../pinctrl-utils.h"
25 #define NS2_NUM_PWM_MUX			4
100  * Northstar2 IOMUX pinctrl core
139  * @pull_shift: pull-up/pull-down control bit shift in the register
182 	NS2_PIN_DESC(0, "mfio_0", -1, 0, 0, 0, 0, 0),
183 	NS2_PIN_DESC(1, "mfio_1", -1, 0, 0, 0, 0, 0),
184 	NS2_PIN_DESC(2, "mfio_2", -1, 0, 0, 0, 0, 0),
185 	NS2_PIN_DESC(3, "mfio_3", -1, 0, 0, 0, 0, 0),
186 	NS2_PIN_DESC(4, "mfio_4", -1, 0, 0, 0, 0, 0),
187 	NS2_PIN_DESC(5, "mfio_5", -1, 0, 0, 0, 0, 0),
188 	NS2_PIN_DESC(6, "mfio_6", -1, 0, 0, 0, 0, 0),
189 	NS2_PIN_DESC(7, "mfio_7", -1, 0, 0, 0, 0, 0),
190 	NS2_PIN_DESC(8, "mfio_8", -1, 0, 0, 0, 0, 0),
191 	NS2_PIN_DESC(9, "mfio_9", -1, 0, 0, 0, 0, 0),
192 	NS2_PIN_DESC(10, "mfio_10", -1, 0, 0, 0, 0, 0),
193 	NS2_PIN_DESC(11, "mfio_11", -1, 0, 0, 0, 0, 0),
194 	NS2_PIN_DESC(12, "mfio_12", -1, 0, 0, 0, 0, 0),
195 	NS2_PIN_DESC(13, "mfio_13", -1, 0, 0, 0, 0, 0),
196 	NS2_PIN_DESC(14, "mfio_14", -1, 0, 0, 0, 0, 0),
197 	NS2_PIN_DESC(15, "mfio_15", -1, 0, 0, 0, 0, 0),
198 	NS2_PIN_DESC(16, "mfio_16", -1, 0, 0, 0, 0, 0),
199 	NS2_PIN_DESC(17, "mfio_17", -1, 0, 0, 0, 0, 0),
200 	NS2_PIN_DESC(18, "mfio_18", -1, 0, 0, 0, 0, 0),
201 	NS2_PIN_DESC(19, "mfio_19", -1, 0, 0, 0, 0, 0),
202 	NS2_PIN_DESC(20, "mfio_20", -1, 0, 0, 0, 0, 0),
203 	NS2_PIN_DESC(21, "mfio_21", -1, 0, 0, 0, 0, 0),
204 	NS2_PIN_DESC(22, "mfio_22", -1, 0, 0, 0, 0, 0),
205 	NS2_PIN_DESC(23, "mfio_23", -1, 0, 0, 0, 0, 0),
206 	NS2_PIN_DESC(24, "mfio_24", -1, 0, 0, 0, 0, 0),
207 	NS2_PIN_DESC(25, "mfio_25", -1, 0, 0, 0, 0, 0),
208 	NS2_PIN_DESC(26, "mfio_26", -1, 0, 0, 0, 0, 0),
209 	NS2_PIN_DESC(27, "mfio_27", -1, 0, 0, 0, 0, 0),
210 	NS2_PIN_DESC(28, "mfio_28", -1, 0, 0, 0, 0, 0),
211 	NS2_PIN_DESC(29, "mfio_29", -1, 0, 0, 0, 0, 0),
212 	NS2_PIN_DESC(30, "mfio_30", -1, 0, 0, 0, 0, 0),
213 	NS2_PIN_DESC(31, "mfio_31", -1, 0, 0, 0, 0, 0),
214 	NS2_PIN_DESC(32, "mfio_32", -1, 0, 0, 0, 0, 0),
215 	NS2_PIN_DESC(33, "mfio_33", -1, 0, 0, 0, 0, 0),
216 	NS2_PIN_DESC(34, "mfio_34", -1, 0, 0, 0, 0, 0),
217 	NS2_PIN_DESC(35, "mfio_35", -1, 0, 0, 0, 0, 0),
218 	NS2_PIN_DESC(36, "mfio_36", -1, 0, 0, 0, 0, 0),
219 	NS2_PIN_DESC(37, "mfio_37", -1, 0, 0, 0, 0, 0),
220 	NS2_PIN_DESC(38, "mfio_38", -1, 0, 0, 0, 0, 0),
221 	NS2_PIN_DESC(39, "mfio_39", -1, 0, 0, 0, 0, 0),
222 	NS2_PIN_DESC(40, "mfio_40", -1, 0, 0, 0, 0, 0),
223 	NS2_PIN_DESC(41, "mfio_41", -1, 0, 0, 0, 0, 0),
224 	NS2_PIN_DESC(42, "mfio_42", -1, 0, 0, 0, 0, 0),
225 	NS2_PIN_DESC(43, "mfio_43", -1, 0, 0, 0, 0, 0),
226 	NS2_PIN_DESC(44, "mfio_44", -1, 0, 0, 0, 0, 0),
227 	NS2_PIN_DESC(45, "mfio_45", -1, 0, 0, 0, 0, 0),
228 	NS2_PIN_DESC(46, "mfio_46", -1, 0, 0, 0, 0, 0),
229 	NS2_PIN_DESC(47, "mfio_47", -1, 0, 0, 0, 0, 0),
230 	NS2_PIN_DESC(48, "mfio_48", -1, 0, 0, 0, 0, 0),
231 	NS2_PIN_DESC(49, "mfio_49", -1, 0, 0, 0, 0, 0),
232 	NS2_PIN_DESC(50, "mfio_50", -1, 0, 0, 0, 0, 0),
233 	NS2_PIN_DESC(51, "mfio_51", -1, 0, 0, 0, 0, 0),
234 	NS2_PIN_DESC(52, "mfio_52", -1, 0, 0, 0, 0, 0),
235 	NS2_PIN_DESC(53, "mfio_53", -1, 0, 0, 0, 0, 0),
236 	NS2_PIN_DESC(54, "mfio_54", -1, 0, 0, 0, 0, 0),
237 	NS2_PIN_DESC(55, "mfio_55", -1, 0, 0, 0, 0, 0),
238 	NS2_PIN_DESC(56, "mfio_56", -1, 0, 0, 0, 0, 0),
239 	NS2_PIN_DESC(57, "mfio_57", -1, 0, 0, 0, 0, 0),
240 	NS2_PIN_DESC(58, "mfio_58", -1, 0, 0, 0, 0, 0),
241 	NS2_PIN_DESC(59, "mfio_59", -1, 0, 0, 0, 0, 0),
242 	NS2_PIN_DESC(60, "mfio_60", -1, 0, 0, 0, 0, 0),
243 	NS2_PIN_DESC(61, "mfio_61", -1, 0, 0, 0, 0, 0),
244 	NS2_PIN_DESC(62, "mfio_62", -1, 0, 0, 0, 0, 0),
307 static const unsigned int nand_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
309 static const unsigned int nor_data_pins[] =  {0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
388 	NS2_PIN_GROUP(uart1_ext_clk, 0, 4, 30, 3, 1),
389 	NS2_PIN_GROUP(nor_adv, 0, 4, 30, 3, 2),
391 	NS2_PIN_GROUP(gpio_2_5,	0, 4, 28, 3, 0),
392 	NS2_PIN_GROUP(pcie_ab1_clk_wak, 0, 4, 28, 3, 1),
393 	NS2_PIN_GROUP(nor_addr_0_3, 0, 4, 28, 3, 2),
395 	NS2_PIN_GROUP(gpio_6_7, 0, 4, 26, 3, 0),
396 	NS2_PIN_GROUP(pcie_a3_clk_wak, 0, 4, 26, 3, 1),
397 	NS2_PIN_GROUP(nor_addr_4_5, 0, 4, 26, 3, 2),
399 	NS2_PIN_GROUP(gpio_8_9, 0, 4, 24, 3, 0),
400 	NS2_PIN_GROUP(pcie_b3_clk_wak, 0, 4, 24, 3, 1),
401 	NS2_PIN_GROUP(nor_addr_6_7, 0, 4, 24, 3, 2),
403 	NS2_PIN_GROUP(gpio_10_11, 0, 4, 22, 3, 0),
404 	NS2_PIN_GROUP(pcie_b2_clk_wak, 0, 4, 22, 3, 1),
405 	NS2_PIN_GROUP(nor_addr_8_9, 0, 4, 22, 3, 2),
407 	NS2_PIN_GROUP(gpio_12_13, 0, 4, 20, 3, 0),
408 	NS2_PIN_GROUP(pcie_a2_clk_wak, 0, 4, 20, 3, 1),
409 	NS2_PIN_GROUP(nor_addr_10_11, 0, 4, 20, 3, 2),
411 	NS2_PIN_GROUP(gpio_14_17, 0, 4, 18, 3, 0),
412 	NS2_PIN_GROUP(uart0_modem, 0, 4, 18, 3, 1),
413 	NS2_PIN_GROUP(nor_addr_12_15, 0, 4, 18, 3, 2),
415 	NS2_PIN_GROUP(gpio_18_19, 0, 4, 16, 3, 0),
416 	NS2_PIN_GROUP(uart0_rts_cts, 0, 4, 16, 3, 1),
418 	NS2_PIN_GROUP(gpio_20_21, 0, 4, 14, 3, 0),
419 	NS2_PIN_GROUP(uart0_in_out, 0, 4, 14, 3, 1),
421 	NS2_PIN_GROUP(gpio_22_23, 0, 4, 12, 3, 0),
422 	NS2_PIN_GROUP(uart1_dcd_dsr, 0, 4, 12, 3, 1),
424 	NS2_PIN_GROUP(gpio_24_25, 0, 4, 10, 3, 0),
425 	NS2_PIN_GROUP(uart1_ri_dtr, 0, 4, 10, 3, 1),
427 	NS2_PIN_GROUP(gpio_26_27, 0, 4, 8, 3, 0),
428 	NS2_PIN_GROUP(uart1_rts_cts, 0, 4, 8, 3, 1),
430 	NS2_PIN_GROUP(gpio_28_29, 0, 4, 6, 3, 0),
431 	NS2_PIN_GROUP(uart1_in_out, 0, 4, 6, 3, 1),
433 	NS2_PIN_GROUP(gpio_30_31, 0, 4, 4, 3, 0),
434 	NS2_PIN_GROUP(uart2_rts_cts, 0, 4, 4, 3, 1),
497 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in ns2_get_groups_count()  local
499 	return pinctrl->num_groups;  in ns2_get_groups_count()
505 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in ns2_get_group_name()  local
507 	return pinctrl->groups[selector].name;  in ns2_get_group_name()
514 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in ns2_get_group_pins()  local
516 	*pins = pinctrl->groups[selector].pins;  in ns2_get_group_pins()
517 	*num_pins = pinctrl->groups[selector].num_pins;  in ns2_get_group_pins()
525 	seq_printf(s, " %s", dev_name(pctrl_dev->dev));  in ns2_pin_dbg_show()
539 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in ns2_get_functions_count()  local
541 	return pinctrl->num_functions;  in ns2_get_functions_count()
547 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in ns2_get_function_name()  local
549 	return pinctrl->functions[selector].name;  in ns2_get_function_name()
557 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in ns2_get_function_groups()  local
559 	*groups = pinctrl->functions[selector].groups;  in ns2_get_function_groups()
560 	*num_groups = pinctrl->functions[selector].num_groups;  in ns2_get_function_groups()
565 static int ns2_pinmux_set(struct ns2_pinctrl *pinctrl,  in ns2_pinmux_set()  argument
570 	const struct ns2_mux *mux = &grp->mux;  in ns2_pinmux_set()
577 		if ((mux->shift != mux_log[i].mux.shift) ||  in ns2_pinmux_set()
578 			(mux->base != mux_log[i].mux.base) ||  in ns2_pinmux_set()
579 			(mux->offset != mux_log[i].mux.offset))  in ns2_pinmux_set()
590 		if (mux_log[i].mux.alt != mux->alt) {  in ns2_pinmux_set()
591 			dev_err(pinctrl->dev,  in ns2_pinmux_set()
593 			dev_err(pinctrl->dev, "func:%s grp:%s\n",  in ns2_pinmux_set()
594 				func->name, grp->name);  in ns2_pinmux_set()
595 			return -EINVAL;  in ns2_pinmux_set()
601 		return -EINVAL;  in ns2_pinmux_set()
603 	mask = mux->mask;  in ns2_pinmux_set()
604 	mux_log[i].mux.alt = mux->alt;  in ns2_pinmux_set()
607 	switch (mux->base) {  in ns2_pinmux_set()
609 		base_address = pinctrl->base0;  in ns2_pinmux_set()
613 		base_address = pinctrl->base1;  in ns2_pinmux_set()
617 		return -EINVAL;  in ns2_pinmux_set()
620 	spin_lock_irqsave(&pinctrl->lock, flags);  in ns2_pinmux_set()
621 	val = readl(base_address + grp->mux.offset);  in ns2_pinmux_set()
622 	val &= ~(mask << grp->mux.shift);  in ns2_pinmux_set()
623 	val |= grp->mux.alt << grp->mux.shift;  in ns2_pinmux_set()
624 	writel(val, (base_address + grp->mux.offset));  in ns2_pinmux_set()
625 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in ns2_pinmux_set()
633 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in ns2_pinmux_enable()  local
637 	if (grp_select >= pinctrl->num_groups ||  in ns2_pinmux_enable()
638 		func_select >= pinctrl->num_functions)  in ns2_pinmux_enable()
639 		return -EINVAL;  in ns2_pinmux_enable()
641 	func = &pinctrl->functions[func_select];  in ns2_pinmux_enable()
642 	grp = &pinctrl->groups[grp_select];  in ns2_pinmux_enable()
644 	dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",  in ns2_pinmux_enable()
645 		func_select, func->name, grp_select, grp->name);  in ns2_pinmux_enable()
647 	dev_dbg(pctrl_dev->dev, "offset:0x%08x shift:%u alt:%u\n",  in ns2_pinmux_enable()
648 		grp->mux.offset, grp->mux.shift, grp->mux.alt);  in ns2_pinmux_enable()
650 	return ns2_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);  in ns2_pinmux_enable()
656 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);  in ns2_pin_set_enable()  local
657 	struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;  in ns2_pin_set_enable()
662 	base_address = pinctrl->pinconf_base;  in ns2_pin_set_enable()
663 	spin_lock_irqsave(&pinctrl->lock, flags);  in ns2_pin_set_enable()
664 	val = readl(base_address + pin_data->pin_conf.offset);  in ns2_pin_set_enable()
665 	val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.input_en);  in ns2_pin_set_enable()
668 		val |= NS2_PIN_INPUT_EN_MASK << pin_data->pin_conf.input_en;  in ns2_pin_set_enable()
670 	writel(val, (base_address + pin_data->pin_conf.offset));  in ns2_pin_set_enable()
671 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in ns2_pin_set_enable()
673 	dev_dbg(pctrldev->dev, "pin:%u set enable:%d\n", pin, enable);  in ns2_pin_set_enable()
679 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);  in ns2_pin_get_enable()  local
680 	struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;  in ns2_pin_get_enable()
684 	spin_lock_irqsave(&pinctrl->lock, flags);  in ns2_pin_get_enable()
685 	enable = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);  in ns2_pin_get_enable()
686 	enable = (enable >> pin_data->pin_conf.input_en) &  in ns2_pin_get_enable()
688 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in ns2_pin_get_enable()
695 	dev_dbg(pctrldev->dev, "pin:%u get disable:%d\n", pin, enable);  in ns2_pin_get_enable()
702 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);  in ns2_pin_set_slew()  local
703 	struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;  in ns2_pin_set_slew()
708 	base_address = pinctrl->pinconf_base;  in ns2_pin_set_slew()
709 	spin_lock_irqsave(&pinctrl->lock, flags);  in ns2_pin_set_slew()
710 	val = readl(base_address + pin_data->pin_conf.offset);  in ns2_pin_set_slew()
711 	val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift);  in ns2_pin_set_slew()
714 		val |= NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift;  in ns2_pin_set_slew()
716 	writel(val, (base_address + pin_data->pin_conf.offset));  in ns2_pin_set_slew()
717 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in ns2_pin_set_slew()
719 	dev_dbg(pctrldev->dev, "pin:%u set slew:%d\n", pin, slew);  in ns2_pin_set_slew()
726 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);  in ns2_pin_get_slew()  local
727 	struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;  in ns2_pin_get_slew()
731 	spin_lock_irqsave(&pinctrl->lock, flags);  in ns2_pin_get_slew()
732 	val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);  in ns2_pin_get_slew()
733 	*slew = (val >> pin_data->pin_conf.src_shift) & NS2_PIN_SRC_MASK;  in ns2_pin_get_slew()
734 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in ns2_pin_get_slew()
736 	dev_dbg(pctrldev->dev, "pin:%u get slew:%d\n", pin, *slew);  in ns2_pin_get_slew()
743 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);  in ns2_pin_set_pull()  local
744 	struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;  in ns2_pin_set_pull()
749 	base_address = pinctrl->pinconf_base;  in ns2_pin_set_pull()
750 	spin_lock_irqsave(&pinctrl->lock, flags);  in ns2_pin_set_pull()
751 	val = readl(base_address + pin_data->pin_conf.offset);  in ns2_pin_set_pull()
752 	val &= ~(NS2_PIN_PULL_MASK << pin_data->pin_conf.pull_shift);  in ns2_pin_set_pull()
755 		val |= NS2_PIN_PULL_UP << pin_data->pin_conf.pull_shift;  in ns2_pin_set_pull()
757 		val |= NS2_PIN_PULL_DOWN << pin_data->pin_conf.pull_shift;  in ns2_pin_set_pull()
758 	writel(val, (base_address + pin_data->pin_conf.offset));  in ns2_pin_set_pull()
759 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in ns2_pin_set_pull()
761 	dev_dbg(pctrldev->dev, "pin:%u set pullup:%d pulldown: %d\n",  in ns2_pin_set_pull()
770 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);  in ns2_pin_get_pull()  local
771 	struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;  in ns2_pin_get_pull()
775 	spin_lock_irqsave(&pinctrl->lock, flags);  in ns2_pin_get_pull()
776 	val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);  in ns2_pin_get_pull()
777 	val = (val >> pin_data->pin_conf.pull_shift) & NS2_PIN_PULL_MASK;  in ns2_pin_get_pull()
786 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in ns2_pin_get_pull()
792 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);  in ns2_pin_set_strength()  local
793 	struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;  in ns2_pin_set_strength()
800 		return -ENOTSUPP;  in ns2_pin_set_strength()
802 	base_address = pinctrl->pinconf_base;  in ns2_pin_set_strength()
803 	spin_lock_irqsave(&pinctrl->lock, flags);  in ns2_pin_set_strength()
804 	val = readl(base_address + pin_data->pin_conf.offset);  in ns2_pin_set_strength()
805 	val &= ~(NS2_PIN_DRIVE_STRENGTH_MASK << pin_data->pin_conf.drive_shift);  in ns2_pin_set_strength()
806 	val |= ((strength / 2) - 1) << pin_data->pin_conf.drive_shift;  in ns2_pin_set_strength()
807 	writel(val, (base_address + pin_data->pin_conf.offset));  in ns2_pin_set_strength()
808 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in ns2_pin_set_strength()
810 	dev_dbg(pctrldev->dev, "pin:%u set drive strength:%d mA\n",  in ns2_pin_set_strength()
818 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);  in ns2_pin_get_strength()  local
819 	struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;  in ns2_pin_get_strength()
823 	spin_lock_irqsave(&pinctrl->lock, flags);  in ns2_pin_get_strength()
824 	val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);  in ns2_pin_get_strength()
825 	*strength = (val >> pin_data->pin_conf.drive_shift) &  in ns2_pin_get_strength()
828 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in ns2_pin_get_strength()
830 	dev_dbg(pctrldev->dev, "pin:%u get drive strength:%d mA\n",  in ns2_pin_get_strength()
838 	struct ns2_pin *pin_data = pctldev->desc->pins[pin].drv_data;  in ns2_pin_config_get()
844 	if (pin_data->pin_conf.base == -1)  in ns2_pin_config_get()
845 		return -ENOTSUPP;  in ns2_pin_config_get()
853 			return -EINVAL;  in ns2_pin_config_get()
860 			return -EINVAL;  in ns2_pin_config_get()
867 			return -EINVAL;  in ns2_pin_config_get()
888 			return -EINVAL;  in ns2_pin_config_get()
891 		return -ENOTSUPP;  in ns2_pin_config_get()
898 	struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;  in ns2_pin_config_set()
902 	int ret = -ENOTSUPP;  in ns2_pin_config_set()
904 	if (pin_data->pin_conf.base == -1)  in ns2_pin_config_set()
905 		return -ENOTSUPP;  in ns2_pin_config_set()
949 			dev_err(pctrldev->dev, "invalid configuration\n");  in ns2_pin_config_set()
950 			return -ENOTSUPP;  in ns2_pin_config_set()
970 	.name = "ns2-pinmux",
976 static int ns2_mux_log_init(struct ns2_pinctrl *pinctrl)  in ns2_mux_log_init()  argument
981 	pinctrl->mux_log = devm_kcalloc(pinctrl->dev, NS2_NUM_IOMUX,  in ns2_mux_log_init()
984 	if (!pinctrl->mux_log)  in ns2_mux_log_init()
985 		return -ENOMEM;  in ns2_mux_log_init()
988 		pinctrl->mux_log[i].is_configured = false;  in ns2_mux_log_init()
990 	log = &pinctrl->mux_log[0];  in ns2_mux_log_init()
991 	log->mux.base = NS2_PIN_MUX_BASE0;  in ns2_mux_log_init()
992 	log->mux.offset = 0;  in ns2_mux_log_init()
993 	log->mux.shift = 31;  in ns2_mux_log_init()
994 	log->mux.alt = 0;  in ns2_mux_log_init()
1001 	for (i = 1; i < (NS2_NUM_IOMUX - NS2_NUM_PWM_MUX); i++) {  in ns2_mux_log_init()
1002 		log = &pinctrl->mux_log[i];  in ns2_mux_log_init()
1003 		log->mux.base = NS2_PIN_MUX_BASE0;  in ns2_mux_log_init()
1004 		log->mux.offset = NS2_MUX_PAD_FUNC1_OFFSET;  in ns2_mux_log_init()
1005 		log->mux.shift = 32 - (i * 2);  in ns2_mux_log_init()
1006 		log->mux.alt = 0;  in ns2_mux_log_init()
1014 		log = &pinctrl->mux_log[(NS2_NUM_IOMUX - NS2_NUM_PWM_MUX) + i];  in ns2_mux_log_init()
1015 		log->mux.base = NS2_PIN_MUX_BASE1;  in ns2_mux_log_init()
1016 		log->mux.offset = 0;  in ns2_mux_log_init()
1017 		log->mux.shift = i;  in ns2_mux_log_init()
1018 		log->mux.alt =  0;  in ns2_mux_log_init()
1025 	struct ns2_pinctrl *pinctrl;  in ns2_pinmux_probe()  local
1031 	pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);  in ns2_pinmux_probe()
1032 	if (!pinctrl)  in ns2_pinmux_probe()
1033 		return -ENOMEM;  in ns2_pinmux_probe()
1035 	pinctrl->dev = &pdev->dev;  in ns2_pinmux_probe()
1036 	platform_set_drvdata(pdev, pinctrl);  in ns2_pinmux_probe()
1037 	spin_lock_init(&pinctrl->lock);  in ns2_pinmux_probe()
1039 	pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);  in ns2_pinmux_probe()
1040 	if (IS_ERR(pinctrl->base0))  in ns2_pinmux_probe()
1041 		return PTR_ERR(pinctrl->base0);  in ns2_pinmux_probe()
1045 		return -EINVAL;  in ns2_pinmux_probe()
1046 	pinctrl->base1 = devm_ioremap(&pdev->dev, res->start,  in ns2_pinmux_probe()
1048 	if (!pinctrl->base1) {  in ns2_pinmux_probe()
1049 		dev_err(&pdev->dev, "unable to map I/O space\n");  in ns2_pinmux_probe()
1050 		return -ENOMEM;  in ns2_pinmux_probe()
1053 	pinctrl->pinconf_base = devm_platform_ioremap_resource(pdev, 2);  in ns2_pinmux_probe()
1054 	if (IS_ERR(pinctrl->pinconf_base))  in ns2_pinmux_probe()
1055 		return PTR_ERR(pinctrl->pinconf_base);  in ns2_pinmux_probe()
1057 	ret = ns2_mux_log_init(pinctrl);  in ns2_pinmux_probe()
1059 		dev_err(&pdev->dev, "unable to initialize IOMUX log\n");  in ns2_pinmux_probe()
1063 	pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);  in ns2_pinmux_probe()
1065 		return -ENOMEM;  in ns2_pinmux_probe()
1073 	pinctrl->groups = ns2_pin_groups;  in ns2_pinmux_probe()
1074 	pinctrl->num_groups = ARRAY_SIZE(ns2_pin_groups);  in ns2_pinmux_probe()
1075 	pinctrl->functions = ns2_pin_functions;  in ns2_pinmux_probe()
1076 	pinctrl->num_functions = ARRAY_SIZE(ns2_pin_functions);  in ns2_pinmux_probe()
1080 	pinctrl->pctl = pinctrl_register(&ns2_pinctrl_desc, &pdev->dev,  in ns2_pinmux_probe()
1081 			pinctrl);  in ns2_pinmux_probe()
1082 	if (IS_ERR(pinctrl->pctl)) {  in ns2_pinmux_probe()
1083 		dev_err(&pdev->dev, "unable to register IOMUX pinctrl\n");  in ns2_pinmux_probe()
1084 		return PTR_ERR(pinctrl->pctl);  in ns2_pinmux_probe()
1091 	{.compatible = "brcm,ns2-pinmux"},
1097 		.name = "ns2-pinmux",