Lines Matching +full:30 +full:ma
212 NS2_PIN_DESC(30, "mfio_30", -1, 0, 0, 0, 0, 0),
245 NS2_PIN_DESC(63, "qspi_wp", 2, 0x0, 31, 30, 27, 24),
249 NS2_PIN_DESC(67, "uart3_sin", 2, 0x04, 31, 30, 27, 24),
253 NS2_PIN_DESC(71, "spi0_fss", 2, 0x08, 31, 30, 27, 24),
257 NS2_PIN_DESC(75, "spi1_fss", 2, 0x0c, 31, 30, 27, 24),
261 NS2_PIN_DESC(79, "sdio0_data7", 2, 0x10, 31, 30, 27, 24),
265 NS2_PIN_DESC(83, "sdio0_data3", 2, 0x14, 31, 30, 27, 24),
269 NS2_PIN_DESC(87, "sdio0_cmd", 2, 0x18, 31, 30, 27, 24),
273 NS2_PIN_DESC(91, "sdio1_led_on", 2, 0x1c, 31, 30, 27, 24),
277 NS2_PIN_DESC(95, "sdio1_data5", 2, 0x20, 31, 30, 27, 24),
281 NS2_PIN_DESC(99, "sdio1_data1", 2, 0x24, 31, 30, 27, 24),
285 NS2_PIN_DESC(103, "sdio1_cd_l", 2, 0x28, 31, 30, 27, 24),
291 NS2_PIN_DESC(109, "usb3_p1_vbus_ppc", 2, 0x34, 31, 30, 27, 24),
295 NS2_PIN_DESC(113, "usb2_presence_indication", 2, 0x38, 31, 30, 27, 24),
319 static const unsigned int gpio_2_5_pins[] = {27, 28, 29, 30};
320 static const unsigned int pcie_ab1_clk_wak_pins[] = {27, 28, 29, 30};
321 static const unsigned int nor_addr_0_3_pins[] = {27, 28, 29, 30};
366 #define NS2_PIN_GROUP(group_name, ba, off, sh, ma, al) \ argument
375 .mask = ma, \
388 NS2_PIN_GROUP(uart1_ext_clk, 0, 4, 30, 3, 1),
389 NS2_PIN_GROUP(nor_adv, 0, 4, 30, 3, 2),
810 dev_dbg(pctrldev->dev, "pin:%u set drive strength:%d mA\n", in ns2_pin_set_strength()
830 dev_dbg(pctrldev->dev, "pin:%u get drive strength:%d mA\n", in ns2_pin_get_strength()
999 * bit position 30. in ns2_mux_log_init()