Lines Matching +full:t +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
13 #include <linux/phy/phy.h>
20 #include <linux/phy/omap_control_phy.h>
216 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
242 /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
267 /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
300 static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy) in ti_pipe3_get_dpll_params() argument
303 struct pipe3_dpll_map *dpll_map = phy->dpll_map; in ti_pipe3_get_dpll_params()
305 rate = clk_get_rate(phy->sys_clk); in ti_pipe3_get_dpll_params()
307 for (; dpll_map->rate; dpll_map++) { in ti_pipe3_get_dpll_params()
308 if (rate == dpll_map->rate) in ti_pipe3_get_dpll_params()
309 return &dpll_map->params; in ti_pipe3_get_dpll_params()
312 dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate); in ti_pipe3_get_dpll_params()
317 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy);
318 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);
320 static int ti_pipe3_power_off(struct phy *x) in ti_pipe3_power_off()
323 struct ti_pipe3 *phy = phy_get_drvdata(x); in ti_pipe3_power_off() local
325 if (!phy->phy_power_syscon) { in ti_pipe3_power_off()
326 omap_control_phy_power(phy->control_dev, 0); in ti_pipe3_power_off()
330 ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg, in ti_pipe3_power_off()
335 static void ti_pipe3_calibrate(struct ti_pipe3 *phy);
337 static int ti_pipe3_power_on(struct phy *x) in ti_pipe3_power_on()
342 struct ti_pipe3 *phy = phy_get_drvdata(x); in ti_pipe3_power_on() local
345 if (!phy->phy_power_syscon) { in ti_pipe3_power_on()
346 omap_control_phy_power(phy->control_dev, 1); in ti_pipe3_power_on()
350 rate = clk_get_rate(phy->sys_clk); in ti_pipe3_power_on()
352 dev_err(phy->dev, "Invalid clock rate\n"); in ti_pipe3_power_on()
353 return -EINVAL; in ti_pipe3_power_on()
358 regmap_update_bits(phy->phy_power_syscon, phy->power_reg, in ti_pipe3_power_on()
365 if (phy->mode == PIPE3_MODE_SATA || phy->mode == PIPE3_MODE_USBSS) { in ti_pipe3_power_on()
372 regmap_update_bits(phy->phy_power_syscon, phy->power_reg, in ti_pipe3_power_on()
377 regmap_update_bits(phy->phy_power_syscon, phy->power_reg, in ti_pipe3_power_on()
381 if (phy->mode == PIPE3_MODE_PCIE) in ti_pipe3_power_on()
382 ti_pipe3_calibrate(phy); in ti_pipe3_power_on()
387 static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy) in ti_pipe3_dpll_wait_lock() argument
395 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); in ti_pipe3_dpll_wait_lock()
400 dev_err(phy->dev, "DPLL failed to lock\n"); in ti_pipe3_dpll_wait_lock()
401 return -EBUSY; in ti_pipe3_dpll_wait_lock()
404 static int ti_pipe3_dpll_program(struct ti_pipe3 *phy) in ti_pipe3_dpll_program() argument
409 dpll_params = ti_pipe3_get_dpll_params(phy); in ti_pipe3_dpll_program()
411 return -EINVAL; in ti_pipe3_dpll_program()
413 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); in ti_pipe3_dpll_program()
415 val |= dpll_params->n << PLL_REGN_SHIFT; in ti_pipe3_dpll_program()
416 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); in ti_pipe3_dpll_program()
418 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); in ti_pipe3_dpll_program()
420 val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; in ti_pipe3_dpll_program()
421 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); in ti_pipe3_dpll_program()
423 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); in ti_pipe3_dpll_program()
425 val |= dpll_params->m << PLL_REGM_SHIFT; in ti_pipe3_dpll_program()
426 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); in ti_pipe3_dpll_program()
428 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); in ti_pipe3_dpll_program()
430 val |= dpll_params->mf << PLL_REGM_F_SHIFT; in ti_pipe3_dpll_program()
431 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); in ti_pipe3_dpll_program()
433 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); in ti_pipe3_dpll_program()
435 val |= dpll_params->sd << PLL_SD_SHIFT; in ti_pipe3_dpll_program()
436 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); in ti_pipe3_dpll_program()
438 ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); in ti_pipe3_dpll_program()
440 return ti_pipe3_dpll_wait_lock(phy); in ti_pipe3_dpll_program()
443 static void ti_pipe3_calibrate(struct ti_pipe3 *phy) in ti_pipe3_calibrate() argument
446 struct pipe3_settings *s = &phy->settings; in ti_pipe3_calibrate()
448 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY); in ti_pipe3_calibrate()
450 val |= (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT); in ti_pipe3_calibrate()
451 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val); in ti_pipe3_calibrate()
453 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES); in ti_pipe3_calibrate()
457 val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT | in ti_pipe3_calibrate()
458 s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT | in ti_pipe3_calibrate()
459 s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT | in ti_pipe3_calibrate()
460 s->dig_lbw << MEM_CDR_LBW_SHIFT | in ti_pipe3_calibrate()
461 s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT | in ti_pipe3_calibrate()
462 s->dig_stl << MEM_CDR_STL_SHIFT | in ti_pipe3_calibrate()
463 s->dig_thr << MEM_CDR_THR_SHIFT | in ti_pipe3_calibrate()
464 s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT | in ti_pipe3_calibrate()
465 s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT; in ti_pipe3_calibrate()
466 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val); in ti_pipe3_calibrate()
468 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM); in ti_pipe3_calibrate()
470 val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT; in ti_pipe3_calibrate()
471 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val); in ti_pipe3_calibrate()
473 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL); in ti_pipe3_calibrate()
475 val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT; in ti_pipe3_calibrate()
476 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val); in ti_pipe3_calibrate()
478 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER); in ti_pipe3_calibrate()
481 val |= s->eq_lev << MEM_EQLEV_SHIFT | in ti_pipe3_calibrate()
482 s->eq_ftc << MEM_EQFTC_SHIFT | in ti_pipe3_calibrate()
483 s->eq_ctl << MEM_EQCTL_SHIFT | in ti_pipe3_calibrate()
484 s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT | in ti_pipe3_calibrate()
485 s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT; in ti_pipe3_calibrate()
486 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val); in ti_pipe3_calibrate()
488 if (phy->mode == PIPE3_MODE_SATA) { in ti_pipe3_calibrate()
489 val = ti_pipe3_readl(phy->phy_rx, in ti_pipe3_calibrate()
492 ti_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES, in ti_pipe3_calibrate()
497 static int ti_pipe3_init(struct phy *x) in ti_pipe3_init()
499 struct ti_pipe3 *phy = phy_get_drvdata(x); in ti_pipe3_init() local
503 ti_pipe3_enable_clocks(phy); in ti_pipe3_init()
505 * Set pcie_pcs register to 0x96 for proper functioning of phy in ti_pipe3_init()
507 * 18-1804. in ti_pipe3_init()
509 if (phy->mode == PIPE3_MODE_PCIE) { in ti_pipe3_init()
510 if (!phy->pcs_syscon) { in ti_pipe3_init()
511 omap_control_pcie_pcs(phy->control_dev, 0x96); in ti_pipe3_init()
516 ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg, in ti_pipe3_init()
522 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); in ti_pipe3_init()
525 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); in ti_pipe3_init()
526 ret = ti_pipe3_dpll_wait_lock(phy); in ti_pipe3_init()
529 /* SATA has issues if re-programmed when locked */ in ti_pipe3_init()
530 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); in ti_pipe3_init()
531 if ((val & PLL_LOCK) && phy->mode == PIPE3_MODE_SATA) in ti_pipe3_init()
535 ret = ti_pipe3_dpll_program(phy); in ti_pipe3_init()
537 ti_pipe3_disable_clocks(phy); in ti_pipe3_init()
538 return -EINVAL; in ti_pipe3_init()
541 ti_pipe3_calibrate(phy); in ti_pipe3_init()
546 static int ti_pipe3_exit(struct phy *x) in ti_pipe3_exit()
548 struct ti_pipe3 *phy = phy_get_drvdata(x); in ti_pipe3_exit() local
555 if (phy->mode == PIPE3_MODE_SATA && !phy->dpll_reset_syscon) in ti_pipe3_exit()
558 /* PCIe doesn't have internal DPLL */ in ti_pipe3_exit()
559 if (phy->mode != PIPE3_MODE_PCIE) { in ti_pipe3_exit()
561 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); in ti_pipe3_exit()
563 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); in ti_pipe3_exit()
569 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); in ti_pipe3_exit()
575 dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n", in ti_pipe3_exit()
577 return -EBUSY; in ti_pipe3_exit()
582 if (phy->mode == PIPE3_MODE_SATA) { in ti_pipe3_exit()
583 regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg, in ti_pipe3_exit()
585 regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg, in ti_pipe3_exit()
589 ti_pipe3_disable_clocks(phy); in ti_pipe3_exit()
603 static int ti_pipe3_get_clk(struct ti_pipe3 *phy) in ti_pipe3_get_clk() argument
606 struct device *dev = phy->dev; in ti_pipe3_get_clk()
608 phy->refclk = devm_clk_get(dev, "refclk"); in ti_pipe3_get_clk()
609 if (IS_ERR(phy->refclk)) { in ti_pipe3_get_clk()
611 /* older DTBs have missing refclk in SATA PHY in ti_pipe3_get_clk()
612 * so don't bail out in case of SATA PHY. in ti_pipe3_get_clk()
614 if (phy->mode != PIPE3_MODE_SATA) in ti_pipe3_get_clk()
615 return PTR_ERR(phy->refclk); in ti_pipe3_get_clk()
618 if (phy->mode != PIPE3_MODE_SATA) { in ti_pipe3_get_clk()
619 phy->wkupclk = devm_clk_get(dev, "wkupclk"); in ti_pipe3_get_clk()
620 if (IS_ERR(phy->wkupclk)) { in ti_pipe3_get_clk()
622 return PTR_ERR(phy->wkupclk); in ti_pipe3_get_clk()
625 phy->wkupclk = ERR_PTR(-ENODEV); in ti_pipe3_get_clk()
628 if (phy->mode != PIPE3_MODE_PCIE || phy->phy_power_syscon) { in ti_pipe3_get_clk()
629 phy->sys_clk = devm_clk_get(dev, "sysclk"); in ti_pipe3_get_clk()
630 if (IS_ERR(phy->sys_clk)) { in ti_pipe3_get_clk()
632 return -EINVAL; in ti_pipe3_get_clk()
636 if (phy->mode == PIPE3_MODE_PCIE) { in ti_pipe3_get_clk()
651 clk = devm_clk_get(dev, "phy-div"); in ti_pipe3_get_clk()
653 dev_err(dev, "unable to get phy-div clk\n"); in ti_pipe3_get_clk()
658 phy->div_clk = devm_clk_get(dev, "div-clk"); in ti_pipe3_get_clk()
659 if (IS_ERR(phy->div_clk)) { in ti_pipe3_get_clk()
660 dev_err(dev, "unable to get div-clk\n"); in ti_pipe3_get_clk()
661 return PTR_ERR(phy->div_clk); in ti_pipe3_get_clk()
664 phy->div_clk = ERR_PTR(-ENODEV); in ti_pipe3_get_clk()
670 static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy) in ti_pipe3_get_sysctrl() argument
672 struct device *dev = phy->dev; in ti_pipe3_get_sysctrl()
673 struct device_node *node = dev->of_node; in ti_pipe3_get_sysctrl()
677 phy->phy_power_syscon = syscon_regmap_lookup_by_phandle(node, in ti_pipe3_get_sysctrl()
678 "syscon-phy-power"); in ti_pipe3_get_sysctrl()
679 if (IS_ERR(phy->phy_power_syscon)) { in ti_pipe3_get_sysctrl()
681 "can't get syscon-phy-power, using control device\n"); in ti_pipe3_get_sysctrl()
682 phy->phy_power_syscon = NULL; in ti_pipe3_get_sysctrl()
685 "syscon-phy-power", 1, in ti_pipe3_get_sysctrl()
686 &phy->power_reg)) { in ti_pipe3_get_sysctrl()
687 dev_err(dev, "couldn't get power reg. offset\n"); in ti_pipe3_get_sysctrl()
688 return -EINVAL; in ti_pipe3_get_sysctrl()
692 if (!phy->phy_power_syscon) { in ti_pipe3_get_sysctrl()
693 control_node = of_parse_phandle(node, "ctrl-module", 0); in ti_pipe3_get_sysctrl()
696 return -EINVAL; in ti_pipe3_get_sysctrl()
703 return -EINVAL; in ti_pipe3_get_sysctrl()
706 phy->control_dev = &control_pdev->dev; in ti_pipe3_get_sysctrl()
709 if (phy->mode == PIPE3_MODE_PCIE) { in ti_pipe3_get_sysctrl()
710 phy->pcs_syscon = syscon_regmap_lookup_by_phandle(node, in ti_pipe3_get_sysctrl()
711 "syscon-pcs"); in ti_pipe3_get_sysctrl()
712 if (IS_ERR(phy->pcs_syscon)) { in ti_pipe3_get_sysctrl()
714 "can't get syscon-pcs, using omap control\n"); in ti_pipe3_get_sysctrl()
715 phy->pcs_syscon = NULL; in ti_pipe3_get_sysctrl()
718 "syscon-pcs", 1, in ti_pipe3_get_sysctrl()
719 &phy->pcie_pcs_reg)) { in ti_pipe3_get_sysctrl()
721 "couldn't get pcie pcs reg. offset\n"); in ti_pipe3_get_sysctrl()
722 return -EINVAL; in ti_pipe3_get_sysctrl()
727 if (phy->mode == PIPE3_MODE_SATA) { in ti_pipe3_get_sysctrl()
728 phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node, in ti_pipe3_get_sysctrl()
729 "syscon-pllreset"); in ti_pipe3_get_sysctrl()
730 if (IS_ERR(phy->dpll_reset_syscon)) { in ti_pipe3_get_sysctrl()
732 "can't get syscon-pllreset, sata dpll won't idle\n"); in ti_pipe3_get_sysctrl()
733 phy->dpll_reset_syscon = NULL; in ti_pipe3_get_sysctrl()
736 "syscon-pllreset", 1, in ti_pipe3_get_sysctrl()
737 &phy->dpll_reset_reg)) { in ti_pipe3_get_sysctrl()
739 "couldn't get pllreset reg. offset\n"); in ti_pipe3_get_sysctrl()
740 return -EINVAL; in ti_pipe3_get_sysctrl()
748 static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy) in ti_pipe3_get_tx_rx_base() argument
750 struct device *dev = phy->dev; in ti_pipe3_get_tx_rx_base()
753 phy->phy_rx = devm_platform_ioremap_resource_byname(pdev, "phy_rx"); in ti_pipe3_get_tx_rx_base()
754 if (IS_ERR(phy->phy_rx)) in ti_pipe3_get_tx_rx_base()
755 return PTR_ERR(phy->phy_rx); in ti_pipe3_get_tx_rx_base()
757 phy->phy_tx = devm_platform_ioremap_resource_byname(pdev, "phy_tx"); in ti_pipe3_get_tx_rx_base()
759 return PTR_ERR_OR_ZERO(phy->phy_tx); in ti_pipe3_get_tx_rx_base()
762 static int ti_pipe3_get_pll_base(struct ti_pipe3 *phy) in ti_pipe3_get_pll_base() argument
764 struct device *dev = phy->dev; in ti_pipe3_get_pll_base()
767 if (phy->mode == PIPE3_MODE_PCIE) in ti_pipe3_get_pll_base()
770 phy->pll_ctrl_base = in ti_pipe3_get_pll_base()
772 return PTR_ERR_OR_ZERO(phy->pll_ctrl_base); in ti_pipe3_get_pll_base()
777 struct ti_pipe3 *phy; in ti_pipe3_probe() local
778 struct phy *generic_phy; in ti_pipe3_probe()
780 struct device *dev = &pdev->dev; in ti_pipe3_probe()
784 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); in ti_pipe3_probe()
785 if (!phy) in ti_pipe3_probe()
786 return -ENOMEM; in ti_pipe3_probe()
790 return -EINVAL; in ti_pipe3_probe()
792 phy->dev = dev; in ti_pipe3_probe()
793 phy->mode = data->mode; in ti_pipe3_probe()
794 phy->dpll_map = data->dpll_map; in ti_pipe3_probe()
795 phy->settings = data->settings; in ti_pipe3_probe()
797 ret = ti_pipe3_get_pll_base(phy); in ti_pipe3_probe()
801 ret = ti_pipe3_get_tx_rx_base(phy); in ti_pipe3_probe()
805 ret = ti_pipe3_get_sysctrl(phy); in ti_pipe3_probe()
809 ret = ti_pipe3_get_clk(phy); in ti_pipe3_probe()
813 platform_set_drvdata(pdev, phy); in ti_pipe3_probe()
817 * Prevent auto-disable of refclk for SATA PHY due to Errata i783 in ti_pipe3_probe()
819 if (phy->mode == PIPE3_MODE_SATA) { in ti_pipe3_probe()
820 if (!IS_ERR(phy->refclk)) { in ti_pipe3_probe()
821 clk_prepare_enable(phy->refclk); in ti_pipe3_probe()
822 phy->sata_refclk_enabled = true; in ti_pipe3_probe()
830 phy_set_drvdata(generic_phy, phy); in ti_pipe3_probe()
840 struct ti_pipe3 *phy = platform_get_drvdata(pdev); in ti_pipe3_remove() local
842 if (phy->mode == PIPE3_MODE_SATA) { in ti_pipe3_remove()
843 clk_disable_unprepare(phy->refclk); in ti_pipe3_remove()
844 phy->sata_refclk_enabled = false; in ti_pipe3_remove()
846 pm_runtime_disable(&pdev->dev); in ti_pipe3_remove()
849 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy) in ti_pipe3_enable_clocks() argument
853 if (!IS_ERR(phy->refclk)) { in ti_pipe3_enable_clocks()
854 ret = clk_prepare_enable(phy->refclk); in ti_pipe3_enable_clocks()
856 dev_err(phy->dev, "Failed to enable refclk %d\n", ret); in ti_pipe3_enable_clocks()
861 if (!IS_ERR(phy->wkupclk)) { in ti_pipe3_enable_clocks()
862 ret = clk_prepare_enable(phy->wkupclk); in ti_pipe3_enable_clocks()
864 dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret); in ti_pipe3_enable_clocks()
869 if (!IS_ERR(phy->div_clk)) { in ti_pipe3_enable_clocks()
870 ret = clk_prepare_enable(phy->div_clk); in ti_pipe3_enable_clocks()
872 dev_err(phy->dev, "Failed to enable div_clk %d\n", ret); in ti_pipe3_enable_clocks()
880 if (!IS_ERR(phy->wkupclk)) in ti_pipe3_enable_clocks()
881 clk_disable_unprepare(phy->wkupclk); in ti_pipe3_enable_clocks()
884 if (!IS_ERR(phy->refclk)) in ti_pipe3_enable_clocks()
885 clk_disable_unprepare(phy->refclk); in ti_pipe3_enable_clocks()
890 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy) in ti_pipe3_disable_clocks() argument
892 if (!IS_ERR(phy->wkupclk)) in ti_pipe3_disable_clocks()
893 clk_disable_unprepare(phy->wkupclk); in ti_pipe3_disable_clocks()
894 if (!IS_ERR(phy->refclk)) in ti_pipe3_disable_clocks()
895 clk_disable_unprepare(phy->refclk); in ti_pipe3_disable_clocks()
896 if (!IS_ERR(phy->div_clk)) in ti_pipe3_disable_clocks()
897 clk_disable_unprepare(phy->div_clk); in ti_pipe3_disable_clocks()
902 .compatible = "ti,phy-usb3",
906 .compatible = "ti,omap-usb3",
910 .compatible = "ti,phy-pipe3-sata",
914 .compatible = "ti,phy-pipe3-pcie",
925 .name = "ti-pipe3",
934 MODULE_DESCRIPTION("TI PIPE3 phy driver");