Lines Matching +full:0 +full:x650
21 #define AM33XX_GMII_SEL_MODE_MII 0
34 PHY_GMII_SEL_PORT_MODE = 0,
76 int ret, rgmii_id = 0; in phy_gmii_sel_mode()
77 u32 gmii_sel_mode = 0; in phy_gmii_sel_mode()
158 return 0; in phy_gmii_sel_mode()
169 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 0, 1),
170 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 4, 4),
171 [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 6, 6),
174 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 2, 3),
175 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 5, 5),
176 [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 7, 7),
191 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 0, 1),
194 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 4, 5),
213 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2), },
214 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2), },
215 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2), },
216 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2), },
217 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2), },
218 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2), },
219 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2), },
220 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2), },
303 int phy_id = args->args[0]; in phy_gmii_sel_of_xlate()
386 return 0; in phy_gmii_init_phy()
400 offset = of_get_address(dev->of_node, 0, &size, NULL); in phy_gmii_sel_init_ports()
416 for (i = 0; i < priv->num_ports; i++) { in phy_gmii_sel_init_ports()
423 return 0; in phy_gmii_sel_init_ports()
449 priv->qsgmii_main_ports = 0; in phy_gmii_sel_probe()
456 for (i = 0; i < soc_data->num_qsgmii_main_ports; i++) { in phy_gmii_sel_probe()
490 return 0; in phy_gmii_sel_probe()
499 for (i = 0; i < priv->num_ports; i++) { in phy_gmii_sel_resume_noirq()
511 return 0; in phy_gmii_sel_resume_noirq()