Lines Matching refs:XUSB_PADCTL_UPHY_PLL_P0_CTL1

170 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360  macro
500 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in tegra210_pex_uphy_enable()
502 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in tegra210_pex_uphy_enable()
522 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in tegra210_pex_uphy_enable()
529 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in tegra210_pex_uphy_enable()
531 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in tegra210_pex_uphy_enable()
533 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in tegra210_pex_uphy_enable()
535 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in tegra210_pex_uphy_enable()
538 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in tegra210_pex_uphy_enable()
584 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in tegra210_pex_uphy_enable()
586 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in tegra210_pex_uphy_enable()
591 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in tegra210_pex_uphy_enable()
648 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in tegra210_pex_uphy_enable()
650 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in tegra210_pex_uphy_enable()