1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * UFS PHY driver for Samsung EXYNOS SoC
13 #include <linux/phy/phy.h>
41 /* UFS PHY registers */
47 /* description for PHY calibration */
76 #define PWR_MODE(g, s, m)	((((g) & GR_MASK) << 4) |\  argument
77 				 (((s) & SR_MASK) << 2) | ((m) & MD_MASK))
80 #define PWR_MODE_HS(g, s)	((((g) & GR_MASK) << 4) |\  argument
81 				 (((s) & SR_MASK) << 2) | PWR_DESC_HS)
86 /* PHY calibration point/state */
115 	/* SoC's specific operations */
116 	int (*wait_for_cal)(struct phy *phy, u8 lane);
117 	int (*wait_for_cdr)(struct phy *phy, u8 lane);
133 static inline struct samsung_ufs_phy *get_samsung_ufs_phy(struct phy *phy)  in get_samsung_ufs_phy()  argument
135 	return (struct samsung_ufs_phy *)phy_get_drvdata(phy);  in get_samsung_ufs_phy()
139 		struct samsung_ufs_phy *phy, u32 isol)  in samsung_ufs_phy_ctrl_isol()  argument
141 	regmap_update_bits(phy->reg_pmu, phy->isol.offset,  in samsung_ufs_phy_ctrl_isol()
142 			   phy->isol.mask, isol ? 0 : phy->isol.en);  in samsung_ufs_phy_ctrl_isol()
145 int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane);