Lines Matching +full:exynos7 +full:- +full:ufs +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0-only
3 * UFS PHY driver for Samsung SoC
17 #include <linux/phy/phy.h>
20 #include <linux/soc/samsung/exynos-pmu.h>
22 #include "phy-samsung-ufs.h"
24 #define for_each_phy_lane(phy, i) \ argument
25 for (i = 0; i < (phy)->lane_cnt; i++)
27 for (; (cfg)->id; (cfg)++)
31 static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy, in samsung_ufs_phy_config() argument
39 writel(cfg->val, (phy)->reg_pma + cfg->off_0); in samsung_ufs_phy_config()
42 if (cfg->id == PHY_TRSV_BLK) in samsung_ufs_phy_config()
43 writel(cfg->val, (phy)->reg_pma + cfg->off_1); in samsung_ufs_phy_config()
48 int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane) in samsung_ufs_phy_wait_for_lock_acq() argument
50 struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy); in samsung_ufs_phy_wait_for_lock_acq()
57 ufs_phy->reg_pma + PHY_APB_ADDR(PHY_PLL_LOCK_STATUS), in samsung_ufs_phy_wait_for_lock_acq()
60 dev_err(ufs_phy->dev, in samsung_ufs_phy_wait_for_lock_acq()
61 "failed to get phy pll lock acquisition %d\n", err); in samsung_ufs_phy_wait_for_lock_acq()
66 ufs_phy->reg_pma + in samsung_ufs_phy_wait_for_lock_acq()
67 PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset), in samsung_ufs_phy_wait_for_lock_acq()
70 dev_err(ufs_phy->dev, in samsung_ufs_phy_wait_for_lock_acq()
71 "failed to get phy cdr lock acquisition %d\n", err); in samsung_ufs_phy_wait_for_lock_acq()
76 static int samsung_ufs_phy_calibrate(struct phy *phy) in samsung_ufs_phy_calibrate() argument
78 struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy); in samsung_ufs_phy_calibrate()
79 const struct samsung_ufs_phy_cfg * const *cfgs = ufs_phy->cfgs; in samsung_ufs_phy_calibrate()
84 if (unlikely(ufs_phy->ufs_phy_state < CFG_PRE_INIT || in samsung_ufs_phy_calibrate()
85 ufs_phy->ufs_phy_state >= CFG_TAG_MAX)) { in samsung_ufs_phy_calibrate()
86 dev_err(ufs_phy->dev, "invalid phy config index %d\n", ufs_phy->ufs_phy_state); in samsung_ufs_phy_calibrate()
87 return -EINVAL; in samsung_ufs_phy_calibrate()
90 cfg = cfgs[ufs_phy->ufs_phy_state]; in samsung_ufs_phy_calibrate()
101 if (ufs_phy->ufs_phy_state == CFG_PRE_INIT && in samsung_ufs_phy_calibrate()
102 ufs_phy->drvdata->wait_for_cal) { in samsung_ufs_phy_calibrate()
103 err = ufs_phy->drvdata->wait_for_cal(phy, i); in samsung_ufs_phy_calibrate()
108 if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS && in samsung_ufs_phy_calibrate()
109 ufs_phy->drvdata->wait_for_cdr) { in samsung_ufs_phy_calibrate()
110 err = ufs_phy->drvdata->wait_for_cdr(phy, i); in samsung_ufs_phy_calibrate()
117 * In Samsung ufshci, PHY need to be calibrated at different in samsung_ufs_phy_calibrate()
120 * Below state machine to make sure to calibrate PHY in each in samsung_ufs_phy_calibrate()
121 * state. Here after configuring PHY in a given state, will in samsung_ufs_phy_calibrate()
122 * change the state to next state so that next state phy in samsung_ufs_phy_calibrate()
126 switch (ufs_phy->ufs_phy_state) { in samsung_ufs_phy_calibrate()
128 ufs_phy->ufs_phy_state = CFG_POST_INIT; in samsung_ufs_phy_calibrate()
131 ufs_phy->ufs_phy_state = CFG_PRE_PWR_HS; in samsung_ufs_phy_calibrate()
134 ufs_phy->ufs_phy_state = CFG_POST_PWR_HS; in samsung_ufs_phy_calibrate()
138 ufs_phy->ufs_phy_state = CFG_PRE_INIT; in samsung_ufs_phy_calibrate()
141 dev_err(ufs_phy->dev, "wrong state for phy calibration\n"); in samsung_ufs_phy_calibrate()
147 static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy) in samsung_ufs_phy_clks_init() argument
150 const struct samsung_ufs_phy_drvdata *drvdata = phy->drvdata; in samsung_ufs_phy_clks_init()
151 int num_clks = drvdata->num_clks; in samsung_ufs_phy_clks_init()
153 phy->clks = devm_kcalloc(phy->dev, num_clks, sizeof(*phy->clks), in samsung_ufs_phy_clks_init()
155 if (!phy->clks) in samsung_ufs_phy_clks_init()
156 return -ENOMEM; in samsung_ufs_phy_clks_init()
159 phy->clks[i].id = drvdata->clk_list[i]; in samsung_ufs_phy_clks_init()
161 return devm_clk_bulk_get(phy->dev, num_clks, phy->clks); in samsung_ufs_phy_clks_init()
164 static int samsung_ufs_phy_init(struct phy *phy) in samsung_ufs_phy_init() argument
166 struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy); in samsung_ufs_phy_init()
168 ss_phy->lane_cnt = phy->attrs.bus_width; in samsung_ufs_phy_init()
169 ss_phy->ufs_phy_state = CFG_PRE_INIT; in samsung_ufs_phy_init()
174 static int samsung_ufs_phy_power_on(struct phy *phy) in samsung_ufs_phy_power_on() argument
176 struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy); in samsung_ufs_phy_power_on()
181 ret = clk_bulk_prepare_enable(ss_phy->drvdata->num_clks, ss_phy->clks); in samsung_ufs_phy_power_on()
183 dev_err(ss_phy->dev, "failed to enable ufs phy clocks\n"); in samsung_ufs_phy_power_on()
187 if (ss_phy->ufs_phy_state == CFG_PRE_INIT) { in samsung_ufs_phy_power_on()
188 ret = samsung_ufs_phy_calibrate(phy); in samsung_ufs_phy_power_on()
190 dev_err(ss_phy->dev, "ufs phy calibration failed\n"); in samsung_ufs_phy_power_on()
196 static int samsung_ufs_phy_power_off(struct phy *phy) in samsung_ufs_phy_power_off() argument
198 struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy); in samsung_ufs_phy_power_off()
200 clk_bulk_disable_unprepare(ss_phy->drvdata->num_clks, ss_phy->clks); in samsung_ufs_phy_power_off()
207 static int samsung_ufs_phy_set_mode(struct phy *generic_phy, in samsung_ufs_phy_set_mode()
212 ss_phy->mode = PHY_MODE_INVALID; in samsung_ufs_phy_set_mode()
215 ss_phy->mode = mode; in samsung_ufs_phy_set_mode()
220 static int samsung_ufs_phy_exit(struct phy *phy) in samsung_ufs_phy_exit() argument
222 struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy); in samsung_ufs_phy_exit()
224 ss_phy->ufs_phy_state = CFG_TAG_MAX; in samsung_ufs_phy_exit()
243 struct device *dev = &pdev->dev; in samsung_ufs_phy_probe()
245 struct samsung_ufs_phy *phy; in samsung_ufs_phy_probe() local
246 struct phy *gen_phy; in samsung_ufs_phy_probe()
252 match = of_match_node(samsung_ufs_phy_match, dev->of_node); in samsung_ufs_phy_probe()
254 err = -EINVAL; in samsung_ufs_phy_probe()
259 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); in samsung_ufs_phy_probe()
260 if (!phy) { in samsung_ufs_phy_probe()
261 err = -ENOMEM; in samsung_ufs_phy_probe()
265 phy->reg_pma = devm_platform_ioremap_resource_byname(pdev, "phy-pma"); in samsung_ufs_phy_probe()
266 if (IS_ERR(phy->reg_pma)) { in samsung_ufs_phy_probe()
267 err = PTR_ERR(phy->reg_pma); in samsung_ufs_phy_probe()
271 phy->reg_pmu = exynos_get_pmu_regmap_by_phandle(dev->of_node, in samsung_ufs_phy_probe()
272 "samsung,pmu-syscon"); in samsung_ufs_phy_probe()
273 if (IS_ERR(phy->reg_pmu)) { in samsung_ufs_phy_probe()
274 err = PTR_ERR(phy->reg_pmu); in samsung_ufs_phy_probe()
282 dev_err(dev, "failed to create PHY for ufs-phy\n"); in samsung_ufs_phy_probe()
286 drvdata = match->data; in samsung_ufs_phy_probe()
287 phy->dev = dev; in samsung_ufs_phy_probe()
288 phy->drvdata = drvdata; in samsung_ufs_phy_probe()
289 phy->cfgs = drvdata->cfgs; in samsung_ufs_phy_probe()
290 memcpy(&phy->isol, &drvdata->isol, sizeof(phy->isol)); in samsung_ufs_phy_probe()
292 if (!of_property_read_u32_index(dev->of_node, "samsung,pmu-syscon", 1, in samsung_ufs_phy_probe()
294 phy->isol.offset = isol_offset; in samsung_ufs_phy_probe()
296 phy->lane_cnt = PHY_DEF_LANE_CNT; in samsung_ufs_phy_probe()
298 err = samsung_ufs_phy_clks_init(phy); in samsung_ufs_phy_probe()
300 dev_err(dev, "failed to get phy clocks\n"); in samsung_ufs_phy_probe()
304 phy_set_drvdata(gen_phy, phy); in samsung_ufs_phy_probe()
309 dev_err(dev, "failed to register phy-provider\n"); in samsung_ufs_phy_probe()
318 .compatible = "google,gs101-ufs-phy",
321 .compatible = "samsung,exynos7-ufs-phy",
324 .compatible = "samsung,exynosautov9-ufs-phy",
327 .compatible = "tesla,fsd-ufs-phy",
337 .name = "samsung-ufs-phy",
342 MODULE_DESCRIPTION("Samsung SoC UFS PHY Driver");