phy/samsung/phy-gs101-ufs.c

11 #define TENSOR_GS101_PHY_CTRL		0x3ec8
12 #define TENSOR_GS101_PHY_CTRL_MASK	0x1
13 #define TENSOR_GS101_PHY_CTRL_EN	BIT(0)
14 #define PHY_GS101_LANE_OFFSET		0x200
15 #define TRSV_REG338			0x338
17 #define TRSV_REG339			0x339
19 #define TRSV_REG222			0x222
31 	PHY_COMN_REG_CFG(0x43, 0x10,  PWR_MODE_ANY),
32 	PHY_COMN_REG_CFG(0x3C, 0x14,  PWR_MODE_ANY),
33 	PHY_COMN_REG_CFG(0x46, 0x48,  PWR_MODE_ANY),
34 	PHY_TRSV_REG_CFG_GS101(0x200, 0x00, PWR_MODE_ANY),
35 	PHY_TRSV_REG_CFG_GS101(0x201, 0x06, PWR_MODE_ANY),
36 	PHY_TRSV_REG_CFG_GS101(0x202, 0x06, PWR_MODE_ANY),
37 	PHY_TRSV_REG_CFG_GS101(0x203, 0x0a, PWR_MODE_ANY),
38 	PHY_TRSV_REG_CFG_GS101(0x204, 0x00, PWR_MODE_ANY),
39 	PHY_TRSV_REG_CFG_GS101(0x205, 0x11, PWR_MODE_ANY),
40 	PHY_TRSV_REG_CFG_GS101(0x207, 0x0c, PWR_MODE_ANY),
41 	PHY_TRSV_REG_CFG_GS101(0x2E1, 0xc0, PWR_MODE_ANY),
42 	PHY_TRSV_REG_CFG_GS101(0x22D, 0xb8, PWR_MODE_ANY),
43 	PHY_TRSV_REG_CFG_GS101(0x234, 0x60, PWR_MODE_ANY),
44 	PHY_TRSV_REG_CFG_GS101(0x238, 0x13, PWR_MODE_ANY),
45 	PHY_TRSV_REG_CFG_GS101(0x239, 0x48, PWR_MODE_ANY),
46 	PHY_TRSV_REG_CFG_GS101(0x23A, 0x01, PWR_MODE_ANY),
47 	PHY_TRSV_REG_CFG_GS101(0x23B, 0x25, PWR_MODE_ANY),
48 	PHY_TRSV_REG_CFG_GS101(0x23C, 0x2a, PWR_MODE_ANY),
49 	PHY_TRSV_REG_CFG_GS101(0x23D, 0x01, PWR_MODE_ANY),
50 	PHY_TRSV_REG_CFG_GS101(0x23E, 0x13, PWR_MODE_ANY),
51 	PHY_TRSV_REG_CFG_GS101(0x23F, 0x13, PWR_MODE_ANY),
52 	PHY_TRSV_REG_CFG_GS101(0x240, 0x4a, PWR_MODE_ANY),
53 	PHY_TRSV_REG_CFG_GS101(0x243, 0x40, PWR_MODE_ANY),
54 	PHY_TRSV_REG_CFG_GS101(0x244, 0x02, PWR_MODE_ANY),
55 	PHY_TRSV_REG_CFG_GS101(0x25D, 0x00, PWR_MODE_ANY),
56 	PHY_TRSV_REG_CFG_GS101(0x25E, 0x3f, PWR_MODE_ANY),
57 	PHY_TRSV_REG_CFG_GS101(0x25F, 0xff, PWR_MODE_ANY),
58 	PHY_TRSV_REG_CFG_GS101(0x273, 0x33, PWR_MODE_ANY),
59 	PHY_TRSV_REG_CFG_GS101(0x274, 0x50, PWR_MODE_ANY),
60 	PHY_TRSV_REG_CFG_GS101(0x284, 0x02, PWR_MODE_ANY),
61 	PHY_TRSV_REG_CFG_GS101(0x285, 0x02, PWR_MODE_ANY),
62 	PHY_TRSV_REG_CFG_GS101(0x2A2, 0x04, PWR_MODE_ANY),
63 	PHY_TRSV_REG_CFG_GS101(0x25D, 0x01, PWR_MODE_ANY),
64 	PHY_TRSV_REG_CFG_GS101(0x2FA, 0x01, PWR_MODE_ANY),
65 	PHY_TRSV_REG_CFG_GS101(0x286, 0x03, PWR_MODE_ANY),
66 	PHY_TRSV_REG_CFG_GS101(0x287, 0x03, PWR_MODE_ANY),
67 	PHY_TRSV_REG_CFG_GS101(0x288, 0x03, PWR_MODE_ANY),
68 	PHY_TRSV_REG_CFG_GS101(0x289, 0x03, PWR_MODE_ANY),
69 	PHY_TRSV_REG_CFG_GS101(0x2B3, 0x04, PWR_MODE_ANY),
70 	PHY_TRSV_REG_CFG_GS101(0x2B6, 0x0b, PWR_MODE_ANY),
71 	PHY_TRSV_REG_CFG_GS101(0x2B7, 0x0b, PWR_MODE_ANY),
72 	PHY_TRSV_REG_CFG_GS101(0x2B8, 0x0b, PWR_MODE_ANY),
73 	PHY_TRSV_REG_CFG_GS101(0x2B9, 0x0b, PWR_MODE_ANY),
74 	PHY_TRSV_REG_CFG_GS101(0x2BA, 0x0b, PWR_MODE_ANY),
75 	PHY_TRSV_REG_CFG_GS101(0x2BB, 0x06, PWR_MODE_ANY),
76 	PHY_TRSV_REG_CFG_GS101(0x2BC, 0x06, PWR_MODE_ANY),
77 	PHY_TRSV_REG_CFG_GS101(0x2BD, 0x06, PWR_MODE_ANY),
78 	PHY_TRSV_REG_CFG_GS101(0x29E, 0x06, PWR_MODE_ANY),
79 	PHY_TRSV_REG_CFG_GS101(0x2E4, 0x1a, PWR_MODE_ANY),
80 	PHY_TRSV_REG_CFG_GS101(0x2ED, 0x25, PWR_MODE_ANY),
81 	PHY_TRSV_REG_CFG_GS101(0x269, 0x1a, PWR_MODE_ANY),
82 	PHY_TRSV_REG_CFG_GS101(0x2F4, 0x2f, PWR_MODE_ANY),
83 	PHY_TRSV_REG_CFG_GS101(0x34B, 0x01, PWR_MODE_ANY),
84 	PHY_TRSV_REG_CFG_GS101(0x34C, 0x23, PWR_MODE_ANY),
85 	PHY_TRSV_REG_CFG_GS101(0x34D, 0x23, PWR_MODE_ANY),
86 	PHY_TRSV_REG_CFG_GS101(0x34E, 0x45, PWR_MODE_ANY),
87 	PHY_TRSV_REG_CFG_GS101(0x34F, 0x00, PWR_MODE_ANY),
88 	PHY_TRSV_REG_CFG_GS101(0x350, 0x31, PWR_MODE_ANY),
89 	PHY_TRSV_REG_CFG_GS101(0x351, 0x00, PWR_MODE_ANY),
90 	PHY_TRSV_REG_CFG_GS101(0x352, 0x02, PWR_MODE_ANY),
91 	PHY_TRSV_REG_CFG_GS101(0x353, 0x00, PWR_MODE_ANY),
92 	PHY_TRSV_REG_CFG_GS101(0x354, 0x01, PWR_MODE_ANY),
93 	PHY_COMN_REG_CFG(0x43, 0x18, PWR_MODE_ANY),
94 	PHY_COMN_REG_CFG(0x43, 0x00, PWR_MODE_ANY),
99 	PHY_TRSV_REG_CFG_GS101(0x369, 0x11, PWR_MODE_ANY),
100 	PHY_TRSV_REG_CFG_GS101(0x246, 0x03, PWR_MODE_ANY),
105 	PHY_COMN_REG_CFG(0x8, 0x60, PWR_MODE_PWM_ANY),
106 	PHY_TRSV_REG_CFG_GS101(0x222, 0x08, PWR_MODE_PWM_ANY),
107 	PHY_TRSV_REG_CFG_GS101(0x246, 0x01, PWR_MODE_ANY),
152 	for (i = 0; i < RETRY_CNT; i++) {  in gs101_phy_wait_for_cdr_lock()
158 			return 0;  in gs101_phy_wait_for_cdr_lock()