Lines Matching +full:0 +full:x042

10 #define FSD_EMBEDDED_COMBO_PHY_CTRL	0x724
11 #define FSD_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
12 #define FSD_EMBEDDED_COMBO_PHY_CTRL_EN	BIT(0)
13 #define FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS	0x6e
16 	PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
17 	PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
18 	PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
19 	PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_ANY),
20 	PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
21 	PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
22 	PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
23 	PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
24 	PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
25 	PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
26 	PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
27 	PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
28 	PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
29 	PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),