Lines Matching +full:0 +full:xfe820000
3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
24 #define PHYREG6 0x14
29 #define PHYREG7 0x18
33 #define PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
34 #define PHYREG7_RX_RTERM_SHIFT 0
37 #define PHYREG8 0x1C
40 #define PHYREG11 0x28
41 #define PHYREG11_SU_TRIM_0_7 0xF0
43 #define PHYREG12 0x2C
46 #define PHYREG13 0x30
48 #define PHYREG13_RESISTER_SHIFT 0x4
52 #define PHYREG14 0x34
53 #define PHYREG14_CKRCV_AMP1 BIT(0)
55 #define PHYREG15 0x38
56 #define PHYREG15_CTLE_EN BIT(0)
61 #define PHYREG16 0x3C
62 #define PHYREG16_SSC_CNT_VALUE 0x5f
64 #define PHYREG18 0x44
65 #define PHYREG18_PLL_LOOP 0x32
67 #define PHYREG27 0x6C
68 #define PHYREG27_RX_TRIM_RK3588 0x4C
70 #define PHYREG32 0x7C
73 #define PHYREG32_SSC_UPWARD 0
78 #define PHYREG33 0x80
233 return 0; in rockchip_combphy_init()
248 return 0; in rockchip_combphy_exit()
266 if (priv->type != PHY_NONE && priv->type != args->args[0]) in rockchip_combphy_xlate()
268 args->args[0], priv->type); in rockchip_combphy_xlate()
270 priv->type = args->args[0]; in rockchip_combphy_xlate()
284 for (i = 0; i < priv->num_clks; i++) { in rockchip_combphy_parse_dt()
316 return 0; in rockchip_combphy_parse_dt()
338 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in rockchip_combphy_probe()
346 for (id = 0; id < phy_cfg->num_phys; id++) { in rockchip_combphy_probe()
406 /* Enable adaptive CTLE for USB3.0 Rx. */ in rk3568_combphy_cfg()
440 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) in rk3568_combphy_cfg()
478 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ in rk3568_combphy_cfg()
540 return 0; in rk3568_combphy_cfg()
545 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
546 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
547 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 },
548 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 },
549 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
550 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
551 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
552 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
553 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
554 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
555 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
556 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
557 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
558 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
559 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
560 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
561 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 },
562 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
563 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
564 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
565 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
566 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
567 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 },
568 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 },
569 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 },
570 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 },
572 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
573 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 },
579 0xfe820000,
580 0xfe830000,
581 0xfe840000,
614 /* Enable adaptive CTLE for USB3.0 Rx. */ in rk3588_combphy_cfg()
646 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) in rk3588_combphy_cfg()
671 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ in rk3588_combphy_cfg()
730 return 0; in rk3588_combphy_cfg()
735 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
736 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
737 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
738 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
739 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
740 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
741 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
742 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
743 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
744 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
745 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
746 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
747 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
748 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
749 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
750 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
751 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
752 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
753 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
754 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
756 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 },
757 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 },
758 .pipe_pcie1l0_sel = { 0x0100, 0, 0, 0x01, 0x0 },
759 .pipe_pcie1l1_sel = { 0x0100, 1, 1, 0x01, 0x0 },
765 0xfee00000,
766 0xfee10000,
767 0xfee20000,