Lines Matching +full:2 +full:-
1 // SPDX-License-Identifier: GPL-2.0+
5 * Author: Zheng Yang <zhengyang@rock-chips.com>
10 #include <linux/clk-provider.h>
16 #include <linux/nvmem-consumer.h>
28 #define RK3228_BYPASS_RXSENSE_EN BIT(2)
45 #define RK3228_RXSENSE_DATA_CH2_ENABLE BIT(2)
74 #define RK3228_PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(3, 2)
75 #define RK3228_PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 3, 2)
97 #define RK3228_TMDS_DATA_CH1_TA(x) UPDATE(x, 3, 2)
102 #define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS_MASK GENMASK(3, 2)
103 #define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS(x) UPDATE(x, 3, 2)
114 #define RK3328_BYPASS_RXSENSE_EN BIT(2)
127 /* for all RK3328_INT_TMDS_*, ESD_DET as defined in 0xc8-0xcb */
129 #define RK3328_INT_RXSENSE_LOW_PULSE_LOCKED BIT(2)
151 #define RK3328_PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(3, 2)
152 #define RK3328_PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 3, 2)
170 #define RK3328_POST_PLL_POST_DIV_ENABLE GENMASK(3, 2)
186 #define RK3328_BANDGAP_ENABLE BIT(2)
189 #define RK3328_TMDS_D2_DRIVER_EN BIT(2)
202 #define RK3328_TERM_RESISTOR_50 UPDATE(0, 2, 1)
203 #define RK3328_TERM_RESISTOR_62_5 UPDATE(1, 2, 1)
204 #define RK3328_TERM_RESISTOR_75 UPDATE(2, 2, 1)
205 #define RK3328_TERM_RESISTOR_100 UPDATE(3, 2, 1)
206 /* REG 0xc8 - 0xcb */
217 #define RK3328_TMDS_TERM_RESIST_600 BIT(2)
296 { 27000000, 27000000, 1, 36, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
298 { 31500000, 31500000, 1, 42, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
300 { 33750000, 33750000, 1, 45, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
301 { 33750000, 42187500, 1, 169, 2, 3, 3, 15, 0, 3, 4, 0, 0x0},
302 { 35500000, 35500000, 1, 71, 2, 2, 2, 6, 0, 3, 4, 0, 0x0},
304 { 36000000, 36000000, 1, 36, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
305 { 36000000, 45000000, 1, 45, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
306 { 40000000, 40000000, 1, 40, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
307 { 40000000, 50000000, 1, 50, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
308 { 49500000, 49500000, 1, 66, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
310 { 50000000, 50000000, 1, 50, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
311 { 50000000, 62500000, 1, 125, 2, 2, 2, 15, 0, 2, 2, 0, 0x0},
312 { 54000000, 54000000, 1, 36, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
313 { 54000000, 67500000, 1, 45, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
314 { 56250000, 56250000, 1, 75, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
316 { 59341000, 59341000, 1, 118, 2, 2, 2, 6, 0, 3, 4, 0, 0xae978d},
317 { 59341000, 74176250, 2, 148, 2, 1, 1, 15, 0, 1, 1, 0, 0x5a3d70},
320 { 65000000, 65000000, 1, 65, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
322 { 68250000, 68250000, 1, 91, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
324 { 71000000, 71000000, 1, 71, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
326 { 72000000, 72000000, 1, 36, 2, 0, 0, 1, 1, 2, 2, 0, 0x0},
327 { 72000000, 90000000, 1, 60, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
328 { 73250000, 73250000, 3, 293, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
329 { 73250000, 91562500, 1, 61, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
330 { 74176000, 74176000, 1, 37, 2, 0, 0, 1, 1, 2, 2, 0, 0x16872b},
331 { 74176000, 92720000, 2, 185, 2, 1, 1, 15, 0, 1, 1, 0, 0x70a3d7},
332 { 74250000, 74250000, 1, 99, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
334 { 75000000, 75000000, 1, 50, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
336 { 78750000, 78750000, 1, 105, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
338 { 79500000, 79500000, 1, 53, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
339 { 79500000, 99375000, 1, 199, 2, 2, 2, 15, 0, 2, 2, 0, 0x0},
340 { 83500000, 83500000, 2, 167, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
341 { 83500000, 104375000, 1, 104, 2, 1, 1, 15, 0, 1, 1, 0, 0x600000},
342 { 85500000, 85500000, 1, 57, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
344 { 85750000, 85750000, 3, 343, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
346 { 88750000, 88750000, 3, 355, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
347 { 88750000, 110937500, 1, 110, 2, 1, 1, 15, 0, 1, 1, 0, 0xf00000},
348 { 94500000, 94500000, 1, 63, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
350 {101000000, 101000000, 1, 101, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
352 {102250000, 102250000, 4, 409, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
353 {102250000, 127812500, 1, 128, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
354 {106500000, 106500000, 1, 71, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
355 {106500000, 133125000, 1, 133, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
356 {108000000, 108000000, 1, 36, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
358 {115500000, 115500000, 1, 77, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
360 {117500000, 117500000, 2, 235, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
362 {119000000, 119000000, 1, 119, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
364 {121750000, 121750000, 4, 487, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
366 {122500000, 122500000, 2, 245, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
368 {135000000, 135000000, 1, 45, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
369 {135000000, 168750000, 1, 169, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
370 {136750000, 136750000, 1, 68, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000},
371 {136750000, 170937500, 1, 113, 0, 2, 2, 1, 3, 2, 2, 0, 0xf5554f},
372 {140250000, 140250000, 2, 187, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
373 {140250000, 175312500, 1, 117, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
374 {146250000, 146250000, 2, 195, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
376 {148250000, 148250000, 3, 222, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000},
377 {148250000, 185312500, 1, 123, 0, 2, 2, 1, 3, 2, 2, 0, 0x8aaab0},
378 {148352000, 148352000, 2, 148, 2, 0, 0, 1, 1, 2, 2, 0, 0x5a1cac},
380 {148500000, 148500000, 1, 99, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
381 {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
382 {154000000, 154000000, 1, 77, 2, 0, 0, 1, 1, 2, 2, 0, 0x0},
384 {156000000, 156000000, 1, 52, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
386 {156750000, 156750000, 2, 209, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
387 {156750000, 195937500, 1, 196, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
388 {157000000, 157000000, 2, 157, 2, 0, 0, 1, 1, 2, 2, 0, 0x0},
389 {157000000, 196250000, 1, 131, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
390 {157500000, 157500000, 1, 105, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
391 {157500000, 196875000, 1, 197, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
392 {162000000, 162000000, 1, 54, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
393 {162000000, 202500000, 2, 135, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
394 {175500000, 175500000, 1, 117, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
396 {179500000, 179500000, 3, 359, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
398 {182750000, 182750000, 1, 91, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000},
399 {182750000, 228437500, 1, 152, 0, 2, 2, 1, 3, 2, 2, 0, 0x4aaab0},
400 {182750000, 228437500, 1, 152, 0, 2, 2, 1, 3, 2, 2, 0, 0x4aaab0},
401 {187000000, 187000000, 2, 187, 2, 0, 0, 1, 1, 2, 2, 0, 0x0},
403 {187250000, 187250000, 3, 280, 2, 0, 0, 1, 1, 2, 2, 0, 0xe00000},
404 {187250000, 234062500, 1, 156, 0, 2, 2, 1, 3, 2, 2, 0, 0xaaab0},
405 {189000000, 189000000, 1, 63, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
407 {193250000, 193250000, 3, 289, 2, 0, 0, 1, 1, 2, 2, 0, 0xe00000},
408 {193250000, 241562500, 1, 161, 0, 2, 2, 1, 3, 2, 2, 0, 0xaaab0},
409 {202500000, 202500000, 2, 135, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
410 {202500000, 253125000, 1, 169, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
411 {204750000, 204750000, 4, 273, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
412 {204750000, 255937500, 1, 171, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
413 {208000000, 208000000, 1, 104, 2, 0, 0, 1, 1, 2, 2, 0, 0x0},
414 {208000000, 260000000, 1, 173, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
415 {214750000, 214750000, 1, 107, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000},
416 {214750000, 268437500, 1, 178, 0, 2, 2, 1, 3, 2, 2, 0, 0xf5554f},
417 {218250000, 218250000, 4, 291, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
419 {229500000, 229500000, 2, 153, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
420 {229500000, 286875000, 1, 191, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
422 {234000000, 292500000, 1, 195, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
423 {241500000, 241500000, 2, 161, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
424 {241500000, 301875000, 1, 201, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
425 {245250000, 245250000, 4, 327, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
427 {245500000, 245500000, 4, 491, 2, 0, 0, 1, 1, 2, 2, 0, 0x0},
429 {261000000, 261000000, 1, 87, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
433 {268500000, 268500000, 2, 179, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
435 {281250000, 281250000, 4, 375, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
438 {288000000, 360000000, 1, 60, 0, 2, 0, 1, 3, 0, 0, 1, 0x0},
441 {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
445 {317000000, 317000000, 3, 317, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
446 {317000000, 396250000, 1, 66, 0, 2, 0, 1, 3, 0, 0, 1, 0x0},
448 {319750000, 399687500, 3, 199, 0, 2, 0, 1, 3, 0, 0, 1, 0xd80000},
451 {348500000, 348500000, 9, 522, 0, 2, 0, 1, 0, 1, 1, 0, 0xc00000},
453 {356500000, 356500000, 9, 534, 0, 2, 0, 1, 0, 1, 1, 0, 0xc00000},
455 {380500000, 380500000, 9, 570, 0, 2, 0, 1, 0, 1, 1, 0, 0xc00000},
457 {443250000, 443250000, 1, 73, 0, 2, 0, 1, 0, 1, 1, 0, 0xe00000},
458 {443250000, 554062500, 1, 92, 0, 2, 0, 1, 3, 0, 0, 1, 0x580000},
459 {505250000, 505250000, 9, 757, 0, 2, 0, 1, 0, 1, 1, 0, 0xe00000},
460 {552750000, 552750000, 3, 276, 0, 2, 0, 1, 0, 1, 1, 0, 0x600000},
463 {593407000, 593407000, 3, 296, 0, 2, 0, 1, 0, 1, 1, 0, 0xb41893},
466 {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0x0},
472 {33750000, 1, 80, 8, 2},
474 {74250000, 18, 80, 8, 2},
475 {148500000, 2, 40, 4, 3},
476 {297000000, 4, 40, 2, 3},
526 * but instead the databook simply numbers the registers in one-increments.
532 regmap_write(inno->regmap, reg * 4, val); in inno_write()
539 regmap_read(inno->regmap, reg * 4, &val); in inno_read()
547 regmap_update_bits(inno->regmap, reg * 4, mask, val); in inno_update_bits()
551 regmap_read_poll_timeout((inno)->regmap, (reg) * 4, val, cond, \
557 int bus_width = phy_get_bus_width(inno->phy); in inno_hdmi_phy_get_tmdsclk()
609 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table; in inno_hdmi_phy_power_on()
611 inno->pixclock); in inno_hdmi_phy_power_on()
615 dev_err(inno->dev, "TMDS clock is zero!\n"); in inno_hdmi_phy_power_on()
616 return -EINVAL; in inno_hdmi_phy_power_on()
619 if (!inno->plat_data->ops->power_on) in inno_hdmi_phy_power_on()
620 return -EINVAL; in inno_hdmi_phy_power_on()
622 for (; cfg->tmdsclock != 0; cfg++) in inno_hdmi_phy_power_on()
623 if (tmdsclock <= cfg->tmdsclock && in inno_hdmi_phy_power_on()
624 cfg->version & inno->chip_version) in inno_hdmi_phy_power_on()
627 for (; phy_cfg->tmdsclock != 0; phy_cfg++) in inno_hdmi_phy_power_on()
628 if (tmdsclock <= phy_cfg->tmdsclock) in inno_hdmi_phy_power_on()
631 if (cfg->tmdsclock == 0 || phy_cfg->tmdsclock == 0) in inno_hdmi_phy_power_on()
632 return -EINVAL; in inno_hdmi_phy_power_on()
634 dev_dbg(inno->dev, "Inno HDMI PHY Power On\n"); in inno_hdmi_phy_power_on()
636 inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000); in inno_hdmi_phy_power_on()
638 ret = clk_prepare_enable(inno->phyclk); in inno_hdmi_phy_power_on()
642 ret = inno->plat_data->ops->power_on(inno, cfg, phy_cfg); in inno_hdmi_phy_power_on()
644 clk_disable_unprepare(inno->phyclk); in inno_hdmi_phy_power_on()
655 if (!inno->plat_data->ops->power_off) in inno_hdmi_phy_power_off()
656 return -EINVAL; in inno_hdmi_phy_power_off()
658 inno->plat_data->ops->power_off(inno); in inno_hdmi_phy_power_off()
660 clk_disable_unprepare(inno->phyclk); in inno_hdmi_phy_power_off()
662 inno->tmdsclock = 0; in inno_hdmi_phy_power_off()
664 dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n"); in inno_hdmi_phy_power_off()
682 for (; cfg->pixclock != 0; cfg++) in inno_hdmi_phy_get_pre_pll_cfg()
683 if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock) in inno_hdmi_phy_get_pre_pll_cfg()
686 if (cfg->pixclock == 0) in inno_hdmi_phy_get_pre_pll_cfg()
687 return ERR_PTR(-EINVAL); in inno_hdmi_phy_get_pre_pll_cfg()
739 no_b += 2; in inno_hdmi_phy_rk3228_clk_recalc_rate()
742 do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2)); in inno_hdmi_phy_rk3228_clk_recalc_rate()
745 inno->pixclock = vco; in inno_hdmi_phy_rk3228_clk_recalc_rate()
747 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); in inno_hdmi_phy_rk3228_clk_recalc_rate()
760 for (; cfg->pixclock != 0; cfg++) in inno_hdmi_phy_rk3228_clk_round_rate()
761 if (cfg->pixclock == rate && !cfg->fracdiv) in inno_hdmi_phy_rk3228_clk_round_rate()
764 if (cfg->pixclock == 0) in inno_hdmi_phy_rk3228_clk_round_rate()
765 return -EINVAL; in inno_hdmi_phy_rk3228_clk_round_rate()
767 return cfg->pixclock; in inno_hdmi_phy_rk3228_clk_round_rate()
780 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", in inno_hdmi_phy_rk3228_clk_set_rate()
783 if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) in inno_hdmi_phy_rk3228_clk_set_rate()
790 /* Power down PRE-PLL */ in inno_hdmi_phy_rk3228_clk_set_rate()
797 RK3228_PRE_PLL_FB_DIV_8(cfg->fbdiv) | in inno_hdmi_phy_rk3228_clk_set_rate()
798 RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en) | in inno_hdmi_phy_rk3228_clk_set_rate()
799 RK3228_PRE_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3228_clk_set_rate()
800 inno_write(inno, 0xe3, RK3228_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_clk_set_rate()
803 RK3228_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b) | in inno_hdmi_phy_rk3228_clk_set_rate()
804 RK3228_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a)); in inno_hdmi_phy_rk3228_clk_set_rate()
807 RK3228_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) | in inno_hdmi_phy_rk3228_clk_set_rate()
808 RK3228_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d)); in inno_hdmi_phy_rk3228_clk_set_rate()
812 RK3228_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) | in inno_hdmi_phy_rk3228_clk_set_rate()
813 RK3228_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) | in inno_hdmi_phy_rk3228_clk_set_rate()
814 RK3228_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b)); in inno_hdmi_phy_rk3228_clk_set_rate()
816 /* Power up PRE-PLL */ in inno_hdmi_phy_rk3228_clk_set_rate()
819 /* Wait for Pre-PLL lock */ in inno_hdmi_phy_rk3228_clk_set_rate()
823 dev_err(inno->dev, "Pre-PLL locking failed\n"); in inno_hdmi_phy_rk3228_clk_set_rate()
827 inno->pixclock = rate; in inno_hdmi_phy_rk3228_clk_set_rate()
828 inno->tmdsclock = tmdsclock; in inno_hdmi_phy_rk3228_clk_set_rate()
895 no_b += 2; in inno_hdmi_phy_rk3328_clk_recalc_rate()
898 do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2)); in inno_hdmi_phy_rk3328_clk_recalc_rate()
901 inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000; in inno_hdmi_phy_rk3328_clk_recalc_rate()
903 dev_dbg(inno->dev, "%s rate %lu vco %llu\n", in inno_hdmi_phy_rk3328_clk_recalc_rate()
904 __func__, inno->pixclock, vco); in inno_hdmi_phy_rk3328_clk_recalc_rate()
906 return inno->pixclock; in inno_hdmi_phy_rk3328_clk_recalc_rate()
917 for (; cfg->pixclock != 0; cfg++) in inno_hdmi_phy_rk3328_clk_round_rate()
918 if (cfg->pixclock == rate) in inno_hdmi_phy_rk3328_clk_round_rate()
921 if (cfg->pixclock == 0) in inno_hdmi_phy_rk3328_clk_round_rate()
922 return -EINVAL; in inno_hdmi_phy_rk3328_clk_round_rate()
924 return cfg->pixclock; in inno_hdmi_phy_rk3328_clk_round_rate()
937 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", in inno_hdmi_phy_rk3328_clk_set_rate()
940 if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) in inno_hdmi_phy_rk3328_clk_set_rate()
950 /* Configure pre-pll */ in inno_hdmi_phy_rk3328_clk_set_rate()
952 RK3328_PCLK_VCO_DIV_5(cfg->vco_div_5_en)); in inno_hdmi_phy_rk3328_clk_set_rate()
953 inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3328_clk_set_rate()
956 if (!cfg->fracdiv) in inno_hdmi_phy_rk3328_clk_set_rate()
958 inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val); in inno_hdmi_phy_rk3328_clk_set_rate()
959 inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3328_clk_set_rate()
960 inno_write(inno, 0xa5, RK3328_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a) | in inno_hdmi_phy_rk3328_clk_set_rate()
961 RK3328_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b)); in inno_hdmi_phy_rk3328_clk_set_rate()
962 inno_write(inno, 0xa6, RK3328_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) | in inno_hdmi_phy_rk3328_clk_set_rate()
963 RK3328_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d)); in inno_hdmi_phy_rk3328_clk_set_rate()
964 inno_write(inno, 0xa4, RK3328_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) | in inno_hdmi_phy_rk3328_clk_set_rate()
965 RK3328_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) | in inno_hdmi_phy_rk3328_clk_set_rate()
966 RK3328_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b)); in inno_hdmi_phy_rk3328_clk_set_rate()
967 inno_write(inno, 0xd3, RK3328_PRE_PLL_FRAC_DIV_7_0(cfg->fracdiv)); in inno_hdmi_phy_rk3328_clk_set_rate()
968 inno_write(inno, 0xd2, RK3328_PRE_PLL_FRAC_DIV_15_8(cfg->fracdiv)); in inno_hdmi_phy_rk3328_clk_set_rate()
969 inno_write(inno, 0xd1, RK3328_PRE_PLL_FRAC_DIV_23_16(cfg->fracdiv)); in inno_hdmi_phy_rk3328_clk_set_rate()
973 /* Wait for Pre-PLL lock */ in inno_hdmi_phy_rk3328_clk_set_rate()
977 dev_err(inno->dev, "Pre-PLL locking failed\n"); in inno_hdmi_phy_rk3328_clk_set_rate()
981 inno->pixclock = rate; in inno_hdmi_phy_rk3328_clk_set_rate()
982 inno->tmdsclock = tmdsclock; in inno_hdmi_phy_rk3328_clk_set_rate()
998 struct device *dev = inno->dev; in inno_hdmi_phy_clk_register()
999 struct device_node *np = dev->of_node; in inno_hdmi_phy_clk_register()
1004 parent_name = __clk_get_name(inno->refoclk); in inno_hdmi_phy_clk_register()
1010 init.ops = inno->plat_data->clk_ops; in inno_hdmi_phy_clk_register()
1013 of_property_read_string(np, "clock-output-names", &init.name); in inno_hdmi_phy_clk_register()
1015 inno->hw.init = &init; in inno_hdmi_phy_clk_register()
1017 inno->phyclk = devm_clk_register(dev, &inno->hw); in inno_hdmi_phy_clk_register()
1018 if (IS_ERR(inno->phyclk)) { in inno_hdmi_phy_clk_register()
1019 ret = PTR_ERR(inno->phyclk); in inno_hdmi_phy_clk_register()
1024 ret = of_clk_add_provider(np, of_clk_src_simple_get, inno->phyclk); in inno_hdmi_phy_clk_register()
1045 /* manual power down post-PLL */ in inno_hdmi_phy_rk3228_init()
1049 inno->chip_version = 1; in inno_hdmi_phy_rk3228_init()
1069 /* Post-PLL update */ in inno_hdmi_phy_rk3228_power_on()
1071 RK3228_POST_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3228_power_on()
1073 RK3228_POST_PLL_FB_DIV_8(cfg->fbdiv)); in inno_hdmi_phy_rk3228_power_on()
1074 inno_write(inno, 0xea, RK3228_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_power_on()
1076 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3228_power_on()
1080 int div = cfg->postdiv / 2 - 1; in inno_hdmi_phy_rk3228_power_on()
1089 inno_write(inno, 0xef + v, phy_cfg->regs[v]); in inno_hdmi_phy_rk3228_power_on()
1102 dev_err(inno->dev, "Post-PLL locking failed\n"); in inno_hdmi_phy_rk3228_power_on()
1106 if (cfg->tmdsclock > 340000000) in inno_hdmi_phy_rk3228_power_on()
1147 /* try to read the chip-version */ in inno_hdmi_phy_rk3328_init()
1148 inno->chip_version = 1; in inno_hdmi_phy_rk3328_init()
1149 cell = nvmem_cell_get(inno->dev, "cpu-version"); in inno_hdmi_phy_rk3328_init()
1151 if (PTR_ERR(cell) == -EPROBE_DEFER) in inno_hdmi_phy_rk3328_init()
1152 return -EPROBE_DEFER; in inno_hdmi_phy_rk3328_init()
1163 inno->chip_version = efuse_buf[0] + 1; in inno_hdmi_phy_rk3328_init()
1181 inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3328_power_on()
1182 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3328_power_on()
1183 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | in inno_hdmi_phy_rk3328_power_on()
1184 RK3328_POST_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3328_power_on()
1188 v = (cfg->postdiv / 2) - 1; in inno_hdmi_phy_rk3328_power_on()
1191 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | in inno_hdmi_phy_rk3328_power_on()
1192 RK3328_POST_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3328_power_on()
1199 inno_write(inno, 0xb5 + v, phy_cfg->regs[v]); in inno_hdmi_phy_rk3328_power_on()
1206 if (phy_cfg->tmdsclock > 340000000) { in inno_hdmi_phy_rk3328_power_on()
1208 v = clk_get_rate(inno->sysclk) / 100000; in inno_hdmi_phy_rk3328_power_on()
1219 if (phy_cfg->tmdsclock > 165000000) in inno_hdmi_phy_rk3328_power_on()
1242 dev_err(inno->dev, "Post-PLL locking failed\n"); in inno_hdmi_phy_rk3328_power_on()
1246 if (phy_cfg->tmdsclock > 340000000) in inno_hdmi_phy_rk3328_power_on()
1300 clk_disable_unprepare(inno->refpclk); in inno_hdmi_phy_action()
1301 clk_disable_unprepare(inno->sysclk); in inno_hdmi_phy_action()
1311 inno = devm_kzalloc(&pdev->dev, sizeof(*inno), GFP_KERNEL); in inno_hdmi_phy_probe()
1313 return -ENOMEM; in inno_hdmi_phy_probe()
1315 inno->dev = &pdev->dev; in inno_hdmi_phy_probe()
1317 inno->plat_data = of_device_get_match_data(inno->dev); in inno_hdmi_phy_probe()
1318 if (!inno->plat_data || !inno->plat_data->ops) in inno_hdmi_phy_probe()
1319 return -EINVAL; in inno_hdmi_phy_probe()
1325 inno->sysclk = devm_clk_get(inno->dev, "sysclk"); in inno_hdmi_phy_probe()
1326 if (IS_ERR(inno->sysclk)) { in inno_hdmi_phy_probe()
1327 ret = PTR_ERR(inno->sysclk); in inno_hdmi_phy_probe()
1328 dev_err(inno->dev, "failed to get sysclk: %d\n", ret); in inno_hdmi_phy_probe()
1332 inno->refpclk = devm_clk_get(inno->dev, "refpclk"); in inno_hdmi_phy_probe()
1333 if (IS_ERR(inno->refpclk)) { in inno_hdmi_phy_probe()
1334 ret = PTR_ERR(inno->refpclk); in inno_hdmi_phy_probe()
1335 dev_err(inno->dev, "failed to get ref clock: %d\n", ret); in inno_hdmi_phy_probe()
1339 inno->refoclk = devm_clk_get(inno->dev, "refoclk"); in inno_hdmi_phy_probe()
1340 if (IS_ERR(inno->refoclk)) { in inno_hdmi_phy_probe()
1341 ret = PTR_ERR(inno->refoclk); in inno_hdmi_phy_probe()
1342 dev_err(inno->dev, "failed to get oscillator-ref clock: %d\n", in inno_hdmi_phy_probe()
1347 ret = clk_prepare_enable(inno->sysclk); in inno_hdmi_phy_probe()
1349 dev_err(inno->dev, "Cannot enable inno phy sysclk: %d\n", ret); in inno_hdmi_phy_probe()
1357 ret = clk_prepare_enable(inno->refpclk); in inno_hdmi_phy_probe()
1359 dev_err(inno->dev, "failed to enable refpclk\n"); in inno_hdmi_phy_probe()
1360 clk_disable_unprepare(inno->sysclk); in inno_hdmi_phy_probe()
1364 ret = devm_add_action_or_reset(inno->dev, inno_hdmi_phy_action, in inno_hdmi_phy_probe()
1369 inno->regmap = devm_regmap_init_mmio(inno->dev, regs, in inno_hdmi_phy_probe()
1371 if (IS_ERR(inno->regmap)) in inno_hdmi_phy_probe()
1372 return PTR_ERR(inno->regmap); in inno_hdmi_phy_probe()
1375 inno->irq = platform_get_irq(pdev, 0); in inno_hdmi_phy_probe()
1376 if (inno->irq > 0) { in inno_hdmi_phy_probe()
1377 ret = devm_request_threaded_irq(inno->dev, inno->irq, in inno_hdmi_phy_probe()
1381 dev_name(inno->dev), inno); in inno_hdmi_phy_probe()
1386 inno->phy = devm_phy_create(inno->dev, NULL, &inno_hdmi_phy_ops); in inno_hdmi_phy_probe()
1387 if (IS_ERR(inno->phy)) { in inno_hdmi_phy_probe()
1388 dev_err(inno->dev, "failed to create HDMI PHY\n"); in inno_hdmi_phy_probe()
1389 return PTR_ERR(inno->phy); in inno_hdmi_phy_probe()
1392 phy_set_drvdata(inno->phy, inno); in inno_hdmi_phy_probe()
1393 phy_set_bus_width(inno->phy, 8); in inno_hdmi_phy_probe()
1395 if (inno->plat_data->ops->init) { in inno_hdmi_phy_probe()
1396 ret = inno->plat_data->ops->init(inno); in inno_hdmi_phy_probe()
1405 phy_provider = devm_of_phy_provider_register(inno->dev, in inno_hdmi_phy_probe()
1412 of_clk_del_provider(pdev->dev.of_node); in inno_hdmi_phy_remove()
1417 .compatible = "rockchip,rk3228-hdmi-phy",
1420 .compatible = "rockchip,rk3328-hdmi-phy",
1430 .name = "inno-hdmi-phy",
1436 MODULE_AUTHOR("Zheng Yang <zhengyang@rock-chips.com>");