Lines Matching +full:px30 +full:- +full:dsi +full:- +full:dphy
1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
12 #include <linux/clk-provider.h>
24 #include <linux/phy/phy-mipi-dphy.h>
290 orig = readl(inno->phy_base + reg); in phy_update_bits()
293 writel(tmp, inno->phy_base + reg); in phy_update_bits()
299 unsigned long prate = clk_get_rate(inno->ref_clk); in inno_dsidphy_pll_calc_rate()
310 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2 in inno_dsidphy_pll_calc_rate()
343 delta = abs(fout - tmp); in inno_dsidphy_pll_calc_rate()
358 inno->pll.prediv = best_prediv; in inno_dsidphy_pll_calc_rate()
359 inno->pll.fbdiv = best_fbdiv; in inno_dsidphy_pll_calc_rate()
360 inno->pll.rate = best_freq; in inno_dsidphy_pll_calc_rate()
368 struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg; in inno_dsidphy_mipi_mode_enable()
376 timings = inno->pdata->inno_mipi_dphy_timing_table; in inno_dsidphy_mipi_mode_enable()
378 inno_dsidphy_pll_calc_rate(inno, cfg->hs_clk_rate); in inno_dsidphy_mipi_mode_enable()
385 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); in inno_dsidphy_mipi_mode_enable()
387 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv)); in inno_dsidphy_mipi_mode_enable()
389 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); in inno_dsidphy_mipi_mode_enable()
390 if (inno->pdata->max_rate == MAX_2_5GHZ) { in inno_dsidphy_mipi_mode_enable()
414 txbyteclkhs = inno->pll.rate / 8; in inno_dsidphy_mipi_mode_enable()
422 * The value of counter for HS Ths-exit in inno_dsidphy_mipi_mode_enable()
423 * Ths-exit = Tpin_txbyteclkhs * value in inno_dsidphy_mipi_mode_enable()
425 hs_exit = DIV_ROUND_UP(cfg->hs_exit, t_txbyteclkhs); in inno_dsidphy_mipi_mode_enable()
427 * The value of counter for HS Tclk-post in inno_dsidphy_mipi_mode_enable()
428 * Tclk-post = Tpin_txbyteclkhs * value in inno_dsidphy_mipi_mode_enable()
430 clk_post = DIV_ROUND_UP(cfg->clk_post, t_txbyteclkhs); in inno_dsidphy_mipi_mode_enable()
432 * The value of counter for HS Tclk-pre in inno_dsidphy_mipi_mode_enable()
433 * Tclk-pre = Tpin_txbyteclkhs * value in inno_dsidphy_mipi_mode_enable()
435 clk_pre = DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE); in inno_dsidphy_mipi_mode_enable()
438 * The value of counter for HS Tta-go in inno_dsidphy_mipi_mode_enable()
439 * Tta-go for turnaround in inno_dsidphy_mipi_mode_enable()
440 * Tta-go = Ttxclkesc * value in inno_dsidphy_mipi_mode_enable()
442 ta_go = DIV_ROUND_UP(cfg->ta_go, t_txclkesc); in inno_dsidphy_mipi_mode_enable()
444 * The value of counter for HS Tta-sure in inno_dsidphy_mipi_mode_enable()
445 * Tta-sure for turnaround in inno_dsidphy_mipi_mode_enable()
446 * Tta-sure = Ttxclkesc * value in inno_dsidphy_mipi_mode_enable()
448 ta_sure = DIV_ROUND_UP(cfg->ta_sure, t_txclkesc); in inno_dsidphy_mipi_mode_enable()
450 * The value of counter for HS Tta-wait in inno_dsidphy_mipi_mode_enable()
451 * Tta-wait for turnaround in inno_dsidphy_mipi_mode_enable()
452 * Tta-wait = Ttxclkesc * value in inno_dsidphy_mipi_mode_enable()
454 ta_wait = DIV_ROUND_UP(cfg->ta_get, t_txclkesc); in inno_dsidphy_mipi_mode_enable()
456 for (i = 0; i < inno->pdata->num_timings; i++) in inno_dsidphy_mipi_mode_enable()
457 if (inno->pll.rate <= timings[i].rate) in inno_dsidphy_mipi_mode_enable()
460 if (i == inno->pdata->num_timings) in inno_dsidphy_mipi_mode_enable()
461 --i; in inno_dsidphy_mipi_mode_enable()
467 if (inno->pdata->max_rate == MAX_1GHZ) { in inno_dsidphy_mipi_mode_enable()
468 lpx = DIV_ROUND_UP(cfg->lpx, t_txbyteclkhs); in inno_dsidphy_mipi_mode_enable()
470 lpx -= 2; in inno_dsidphy_mipi_mode_enable()
490 if (inno->pdata->max_rate == MAX_2_5GHZ) in inno_dsidphy_mipi_mode_enable()
497 if (inno->pdata->max_rate == MAX_2_5GHZ) in inno_dsidphy_mipi_mode_enable()
502 if (inno->pdata->max_rate == MAX_2_5GHZ) in inno_dsidphy_mipi_mode_enable()
583 clk_prepare_enable(inno->pclk_phy); in inno_dsidphy_power_on()
584 clk_prepare_enable(inno->ref_clk); in inno_dsidphy_power_on()
585 pm_runtime_get_sync(inno->dev); in inno_dsidphy_power_on()
594 switch (inno->mode) { in inno_dsidphy_power_on()
602 return -EINVAL; in inno_dsidphy_power_on()
629 pm_runtime_put(inno->dev); in inno_dsidphy_power_off()
630 clk_disable_unprepare(inno->ref_clk); in inno_dsidphy_power_off()
631 clk_disable_unprepare(inno->pclk_phy); in inno_dsidphy_power_off()
644 inno->mode = mode; in inno_dsidphy_set_mode()
647 return -EINVAL; in inno_dsidphy_set_mode()
659 if (inno->mode != PHY_MODE_MIPI_DPHY) in inno_dsidphy_configure()
660 return -EINVAL; in inno_dsidphy_configure()
662 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); in inno_dsidphy_configure()
666 memcpy(&inno->dphy_cfg, &opts->mipi_dphy, sizeof(inno->dphy_cfg)); in inno_dsidphy_configure()
693 struct device *dev = &pdev->dev; in inno_dsidphy_probe()
701 return -ENOMEM; in inno_dsidphy_probe()
703 inno->dev = dev; in inno_dsidphy_probe()
704 inno->pdata = of_device_get_match_data(inno->dev); in inno_dsidphy_probe()
707 inno->phy_base = devm_platform_ioremap_resource(pdev, 0); in inno_dsidphy_probe()
708 if (IS_ERR(inno->phy_base)) in inno_dsidphy_probe()
709 return PTR_ERR(inno->phy_base); in inno_dsidphy_probe()
711 inno->ref_clk = devm_clk_get(dev, "ref"); in inno_dsidphy_probe()
712 if (IS_ERR(inno->ref_clk)) { in inno_dsidphy_probe()
713 ret = PTR_ERR(inno->ref_clk); in inno_dsidphy_probe()
718 inno->pclk_phy = devm_clk_get(dev, "pclk"); in inno_dsidphy_probe()
719 if (IS_ERR(inno->pclk_phy)) { in inno_dsidphy_probe()
720 ret = PTR_ERR(inno->pclk_phy); in inno_dsidphy_probe()
725 inno->rst = devm_reset_control_get(dev, "apb"); in inno_dsidphy_probe()
726 if (IS_ERR(inno->rst)) { in inno_dsidphy_probe()
727 ret = PTR_ERR(inno->rst); in inno_dsidphy_probe()
757 pm_runtime_disable(inno->dev); in inno_dsidphy_remove()
762 .compatible = "rockchip,px30-dsi-dphy",
765 .compatible = "rockchip,rk3128-dsi-dphy",
768 .compatible = "rockchip,rk3368-dsi-dphy",
771 .compatible = "rockchip,rk3568-dsi-dphy",
774 .compatible = "rockchip,rv1126-dsi-dphy",
783 .name = "inno-dsidphy",
791 MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");