Lines Matching +full:tcsr +full:- +full:reg
1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/nvmem-consumer.h>
22 #include <dt-bindings/phy/phy-qcom-qusb2.h>
105 * if yes, then offset gives index in the reg-layout
123 /* set of registers with offsets different per-PHY */
276 /* offset to PHY_CLK_SCHEME register in TCSR map */
294 /* true if PHY default clk scheme is single-ended */
373 "vdd", "vdda-pll", "vdda-phy-dpdm",
378 /* struct override_param - structure holding qusb2 v2 phy overriding param
387 /*struct override_params - structure holding qusb2 v2 phy overriding params
390 * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register
391 * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
407 * struct qusb2_phy - structure holding qusb2 phy attributes
418 * @tcsr: TCSR syscon register map
424 * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
438 struct regmap *tcsr; member
452 u32 reg; in qusb2_write_mask() local
454 reg = readl(base + offset); in qusb2_write_mask()
455 reg &= ~mask; in qusb2_write_mask()
456 reg |= val & mask; in qusb2_write_mask()
457 writel(reg, base + offset); in qusb2_write_mask()
465 u32 reg; in qusb2_setbits() local
467 reg = readl(base + offset); in qusb2_setbits()
468 reg |= val; in qusb2_setbits()
469 writel(reg, base + offset); in qusb2_setbits()
477 u32 reg; in qusb2_clrbits() local
479 reg = readl(base + offset); in qusb2_clrbits()
480 reg &= ~val; in qusb2_clrbits()
481 writel(reg, base + offset); in qusb2_clrbits()
508 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_override_phy_params()
509 struct override_params *or = &qphy->overrides; in qusb2_phy_override_phy_params()
511 if (or->imp_res_offset.override) in qusb2_phy_override_phy_params()
512 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1, in qusb2_phy_override_phy_params()
513 or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
516 if (or->bias_ctrl.override) in qusb2_phy_override_phy_params()
517 qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2, in qusb2_phy_override_phy_params()
518 or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
521 if (or->charge_ctrl.override) in qusb2_phy_override_phy_params()
522 qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2, in qusb2_phy_override_phy_params()
523 or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
526 if (or->hstx_trim.override) in qusb2_phy_override_phy_params()
527 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
528 or->hstx_trim.value << HSTX_TRIM_SHIFT, in qusb2_phy_override_phy_params()
531 if (or->preemphasis.override) in qusb2_phy_override_phy_params()
532 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
533 or->preemphasis.value << PREEMPHASIS_EN_SHIFT, in qusb2_phy_override_phy_params()
536 if (or->preemphasis_width.override) { in qusb2_phy_override_phy_params()
537 if (or->preemphasis_width.value == in qusb2_phy_override_phy_params()
539 qusb2_setbits(qphy->base, in qusb2_phy_override_phy_params()
540 cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
543 qusb2_clrbits(qphy->base, in qusb2_phy_override_phy_params()
544 cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
548 if (or->hsdisc_trim.override) in qusb2_phy_override_phy_params()
549 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], in qusb2_phy_override_phy_params()
550 or->hsdisc_trim.value << HSDISC_TRIM_SHIFT, in qusb2_phy_override_phy_params()
561 struct device *dev = &qphy->phy->dev; in qusb2_phy_set_tune2_param()
562 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_set_tune2_param()
566 if (!qphy->cell) in qusb2_phy_set_tune2_param()
576 val = nvmem_cell_read(qphy->cell, NULL); in qusb2_phy_set_tune2_param()
578 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); in qusb2_phy_set_tune2_param()
584 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); in qusb2_phy_set_tune2_param()
589 if (cfg->update_tune1_with_efuse) in qusb2_phy_set_tune2_param()
590 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_set_tune2_param()
593 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], in qusb2_phy_set_tune2_param()
602 qphy->mode = mode; in qusb2_phy_set_mode()
610 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_runtime_suspend()
613 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode); in qusb2_phy_runtime_suspend()
615 if (!qphy->phy_initialized) { in qusb2_phy_runtime_suspend()
623 * current D+/D- levels are e.g. if currently D+ high, D- low in qusb2_phy_runtime_suspend()
624 * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high in qusb2_phy_runtime_suspend()
627 switch (qphy->mode) { in qusb2_phy_runtime_suspend()
645 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); in qusb2_phy_runtime_suspend()
648 if (cfg->has_pll_override) { in qusb2_phy_runtime_suspend()
649 qusb2_setbits(qphy->base, in qusb2_phy_runtime_suspend()
650 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], in qusb2_phy_runtime_suspend()
655 /* enable phy auto-resume only if device is connected on bus */ in qusb2_phy_runtime_suspend()
656 if (qphy->mode != PHY_MODE_INVALID) { in qusb2_phy_runtime_suspend()
657 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], in qusb2_phy_runtime_suspend()
658 cfg->autoresume_en); in qusb2_phy_runtime_suspend()
660 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], in qusb2_phy_runtime_suspend()
661 cfg->autoresume_en); in qusb2_phy_runtime_suspend()
664 if (!qphy->has_se_clk_scheme) in qusb2_phy_runtime_suspend()
665 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_runtime_suspend()
667 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_runtime_suspend()
668 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_runtime_suspend()
676 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_runtime_resume()
679 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode); in qusb2_phy_runtime_resume()
681 if (!qphy->phy_initialized) { in qusb2_phy_runtime_resume()
686 ret = clk_prepare_enable(qphy->iface_clk); in qusb2_phy_runtime_resume()
692 ret = clk_prepare_enable(qphy->cfg_ahb_clk); in qusb2_phy_runtime_resume()
698 if (!qphy->has_se_clk_scheme) { in qusb2_phy_runtime_resume()
699 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_runtime_resume()
706 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); in qusb2_phy_runtime_resume()
709 if (cfg->has_pll_override) { in qusb2_phy_runtime_resume()
710 qusb2_clrbits(qphy->base, in qusb2_phy_runtime_resume()
711 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], in qusb2_phy_runtime_resume()
718 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_runtime_resume()
720 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_runtime_resume()
728 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_init()
733 dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__); in qusb2_phy_init()
736 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_init()
740 ret = clk_prepare_enable(qphy->iface_clk); in qusb2_phy_init()
742 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret); in qusb2_phy_init()
747 ret = clk_prepare_enable(qphy->cfg_ahb_clk); in qusb2_phy_init()
749 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); in qusb2_phy_init()
754 ret = reset_control_assert(qphy->phy_reset); in qusb2_phy_init()
756 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); in qusb2_phy_init()
763 ret = reset_control_deassert(qphy->phy_reset); in qusb2_phy_init()
765 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); in qusb2_phy_init()
770 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_init()
771 qphy->cfg->disable_ctrl); in qusb2_phy_init()
773 if (cfg->has_pll_test) { in qusb2_phy_init()
775 val = readl(qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
778 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, in qusb2_phy_init()
779 cfg->tbl_num); in qusb2_phy_init()
788 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_init()
796 * register in the TCSR so, if there's none, use the default in qusb2_phy_init()
799 qphy->has_se_clk_scheme = cfg->se_clk_scheme_default; in qusb2_phy_init()
802 * read TCSR_PHY_CLK_SCHEME register to check if single-ended in qusb2_phy_init()
804 * ref_clk and use single-ended clock, otherwise use differential in qusb2_phy_init()
807 if (qphy->tcsr) { in qusb2_phy_init()
808 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, in qusb2_phy_init()
811 dev_err(&phy->dev, "failed to read clk scheme reg\n"); in qusb2_phy_init()
817 dev_vdbg(&phy->dev, "%s(): select differential clk\n", in qusb2_phy_init()
819 qphy->has_se_clk_scheme = false; in qusb2_phy_init()
821 dev_vdbg(&phy->dev, "%s(): select single-ended clk\n", in qusb2_phy_init()
826 if (!qphy->has_se_clk_scheme) { in qusb2_phy_init()
827 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_init()
829 dev_err(&phy->dev, "failed to enable ref clk, %d\n", in qusb2_phy_init()
835 if (cfg->has_pll_test) { in qusb2_phy_init()
836 if (!qphy->has_se_clk_scheme) in qusb2_phy_init()
841 writel(val, qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
844 readl(qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
850 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); in qusb2_phy_init()
851 if (!(val & cfg->mask_core_ready)) { in qusb2_phy_init()
852 dev_err(&phy->dev, in qusb2_phy_init()
853 "QUSB2PHY pll lock failed: status reg = %x\n", val); in qusb2_phy_init()
854 ret = -EBUSY; in qusb2_phy_init()
857 qphy->phy_initialized = true; in qusb2_phy_init()
862 if (!qphy->has_se_clk_scheme) in qusb2_phy_init()
863 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_init()
865 reset_control_assert(qphy->phy_reset); in qusb2_phy_init()
867 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_init()
869 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_init()
871 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_init()
881 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_exit()
882 qphy->cfg->disable_ctrl); in qusb2_phy_exit()
884 if (!qphy->has_se_clk_scheme) in qusb2_phy_exit()
885 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_exit()
887 reset_control_assert(qphy->phy_reset); in qusb2_phy_exit()
889 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_exit()
890 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_exit()
892 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_exit()
894 qphy->phy_initialized = false; in qusb2_phy_exit()
908 .compatible = "qcom,ipq6018-qusb2-phy",
911 .compatible = "qcom,ipq8074-qusb2-phy",
914 .compatible = "qcom,ipq9574-qusb2-phy",
917 .compatible = "qcom,msm8953-qusb2-phy",
920 .compatible = "qcom,msm8996-qusb2-phy",
923 .compatible = "qcom,msm8998-qusb2-phy",
926 .compatible = "qcom,qcm2290-qusb2-phy",
929 .compatible = "qcom,sdm660-qusb2-phy",
932 .compatible = "qcom,sm4250-qusb2-phy",
935 .compatible = "qcom,sm6115-qusb2-phy",
940 * trees that didn't include "qcom,qusb2-v2-phy"
942 .compatible = "qcom,sdm845-qusb2-phy",
945 .compatible = "qcom,qusb2-v2-phy",
959 struct device *dev = &pdev->dev; in qusb2_phy_probe()
970 return -ENOMEM; in qusb2_phy_probe()
971 or = &qphy->overrides; in qusb2_phy_probe()
973 qphy->base = devm_platform_ioremap_resource(pdev, 0); in qusb2_phy_probe()
974 if (IS_ERR(qphy->base)) in qusb2_phy_probe()
975 return PTR_ERR(qphy->base); in qusb2_phy_probe()
977 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb"); in qusb2_phy_probe()
978 if (IS_ERR(qphy->cfg_ahb_clk)) in qusb2_phy_probe()
979 return dev_err_probe(dev, PTR_ERR(qphy->cfg_ahb_clk), in qusb2_phy_probe()
982 qphy->ref_clk = devm_clk_get(dev, "ref"); in qusb2_phy_probe()
983 if (IS_ERR(qphy->ref_clk)) in qusb2_phy_probe()
984 return dev_err_probe(dev, PTR_ERR(qphy->ref_clk), in qusb2_phy_probe()
987 qphy->iface_clk = devm_clk_get_optional(dev, "iface"); in qusb2_phy_probe()
988 if (IS_ERR(qphy->iface_clk)) in qusb2_phy_probe()
989 return PTR_ERR(qphy->iface_clk); in qusb2_phy_probe()
991 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0); in qusb2_phy_probe()
992 if (IS_ERR(qphy->phy_reset)) { in qusb2_phy_probe()
994 return PTR_ERR(qphy->phy_reset); in qusb2_phy_probe()
997 num = ARRAY_SIZE(qphy->vregs); in qusb2_phy_probe()
999 qphy->vregs[i].supply = qusb2_phy_vreg_names[i]; in qusb2_phy_probe()
1001 ret = devm_regulator_bulk_get(dev, num, qphy->vregs); in qusb2_phy_probe()
1007 qphy->cfg = of_device_get_match_data(dev); in qusb2_phy_probe()
1009 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, in qusb2_phy_probe()
1010 "qcom,tcsr-syscon"); in qusb2_phy_probe()
1011 if (IS_ERR(qphy->tcsr)) { in qusb2_phy_probe()
1012 dev_dbg(dev, "failed to lookup TCSR regmap\n"); in qusb2_phy_probe()
1013 qphy->tcsr = NULL; in qusb2_phy_probe()
1016 qphy->cell = devm_nvmem_cell_get(dev, NULL); in qusb2_phy_probe()
1017 if (IS_ERR(qphy->cell)) { in qusb2_phy_probe()
1018 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER) in qusb2_phy_probe()
1019 return -EPROBE_DEFER; in qusb2_phy_probe()
1020 qphy->cell = NULL; in qusb2_phy_probe()
1024 if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value", in qusb2_phy_probe()
1026 or->imp_res_offset.value = (u8)value; in qusb2_phy_probe()
1027 or->imp_res_offset.override = true; in qusb2_phy_probe()
1030 if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value", in qusb2_phy_probe()
1032 or->bias_ctrl.value = (u8)value; in qusb2_phy_probe()
1033 or->bias_ctrl.override = true; in qusb2_phy_probe()
1036 if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value", in qusb2_phy_probe()
1038 or->charge_ctrl.value = (u8)value; in qusb2_phy_probe()
1039 or->charge_ctrl.override = true; in qusb2_phy_probe()
1042 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value", in qusb2_phy_probe()
1044 or->hstx_trim.value = (u8)value; in qusb2_phy_probe()
1045 or->hstx_trim.override = true; in qusb2_phy_probe()
1048 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level", in qusb2_phy_probe()
1050 or->preemphasis.value = (u8)value; in qusb2_phy_probe()
1051 or->preemphasis.override = true; in qusb2_phy_probe()
1054 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width", in qusb2_phy_probe()
1056 or->preemphasis_width.value = (u8)value; in qusb2_phy_probe()
1057 or->preemphasis_width.override = true; in qusb2_phy_probe()
1060 if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value", in qusb2_phy_probe()
1062 or->hsdisc_trim.value = (u8)value; in qusb2_phy_probe()
1063 or->hsdisc_trim.override = true; in qusb2_phy_probe()
1081 qphy->phy = generic_phy; in qusb2_phy_probe()
1088 dev_info(dev, "Registered Qcom-QUSB2 phy\n"); in qusb2_phy_probe()
1098 .name = "qcom-qusb2-phy",