Lines Matching +full:0 +full:x240
10 #define QPHY_V6_PCS_UFS_PHY_START 0x000
11 #define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V6_PCS_UFS_SW_RESET 0x008
13 #define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
14 #define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
15 #define QPHY_V6_PCS_UFS_PCS_CTRL1 0x020
16 #define QPHY_V6_PCS_UFS_PLL_CNTL 0x02c
17 #define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
18 #define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
19 #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
20 #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
21 #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
22 #define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
23 #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
24 #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
25 #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
26 #define QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2 0x18c
27 #define QPHY_V6_PCS_UFS_TX_PWM_GEAR_BAND 0x178
28 #define QPHY_V6_PCS_UFS_TX_HS_GEAR_BAND 0x174
29 #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
30 #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
31 #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
32 #define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
33 #define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4 0x240
34 #define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5 0x244
35 #define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6 0x248
36 #define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7 0x24c