Lines Matching +full:tx +full:- +full:pcs
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
25 #include <dt-bindings/phy/phy-qcom-qmp.h>
27 #include "phy-qcom-qmp-common.h"
29 #include "phy-qcom-qmp.h"
30 #include "phy-qcom-qmp-pcs-misc-v3.h"
31 #include "phy-qcom-qmp-pcs-pcie-v4.h"
32 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
33 #include "phy-qcom-qmp-pcs-pcie-v5.h"
34 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
35 #include "phy-qcom-qmp-pcs-pcie-v6.h"
36 #include "phy-qcom-qmp-pcs-pcie-v6_20.h"
37 #include "phy-qcom-qmp-pcie-qhp.h"
41 /* set of registers with offsets different per-PHY */
43 /* PCS registers */
2579 u16 pcs; member
2581 u16 tx; member
2591 const struct qmp_phy_init_tbl *tx; member
2595 const struct qmp_phy_init_tbl *pcs; member
2603 /* struct qmp_phy_cfg - per-PHY initialization config */
2609 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
2656 void __iomem *pcs; member
2658 void __iomem *tx; member
2712 "vdda-phy", "vdda-pll",
2716 "vdda-phy", "vdda-pll", "vdda-qref",
2730 .pcs = 0x1800,
2731 .tx = 0x0800,
2737 .pcs = 0x0800,
2738 .tx = 0x0200,
2744 .pcs = 0x0800,
2746 .tx = 0x0200,
2752 .pcs = 0x0800,
2754 .tx = 0x0200,
2760 .pcs = 0x0a00,
2762 .tx = 0x0200,
2770 .pcs = 0x1200,
2772 .tx = 0x0000,
2780 .pcs = 0x0200,
2782 .tx = 0x0e00,
2790 .pcs = 0x1000,
2792 .tx = 0x0200,
2800 .pcs = 0x1200,
2802 .tx = 0x0000,
2810 .pcs = 0x2200,
2812 .tx = 0x0,
2820 .pcs = 0x1200,
2822 .tx = 0x0000,
2837 .tx = ipq8074_pcie_tx_tbl,
2841 .pcs = ipq8074_pcie_pcs_tbl,
2862 .tx = ipq8074_pcie_gen3_tx_tbl,
2866 .pcs = ipq8074_pcie_gen3_pcs_tbl,
2891 .tx = ipq6018_pcie_tx_tbl,
2895 .pcs = ipq6018_pcie_pcs_tbl,
2918 .tx = ipq8074_pcie_gen3_tx_tbl,
2922 .pcs = ipq9574_gen3x1_pcie_pcs_tbl,
2946 .tx = ipq8074_pcie_gen3_tx_tbl,
2950 .pcs = ipq9574_gen3x2_pcie_pcs_tbl,
2974 .tx = sdm845_qmp_pcie_tx_tbl,
2978 .pcs = sdm845_qmp_pcie_pcs_tbl,
3001 .tx = sdm845_qhp_pcie_tx_tbl,
3003 .pcs = sdm845_qhp_pcie_pcs_tbl,
3024 .tx = sm8250_qmp_pcie_tx_tbl,
3028 .pcs = sm8250_qmp_pcie_pcs_tbl,
3038 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl,
3061 .tx = sm8250_qmp_pcie_tx_tbl,
3065 .pcs = sm8250_qmp_pcie_pcs_tbl,
3071 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl,
3075 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl,
3098 .tx = msm8998_pcie_tx_tbl,
3102 .pcs = msm8998_pcie_pcs_tbl,
3125 .tx = sc8180x_qmp_pcie_tx_tbl,
3129 .pcs = sc8180x_qmp_pcie_pcs_tbl,
3152 .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl,
3156 .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl,
3185 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
3189 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
3218 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
3222 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
3254 .tx = sdx55_qmp_pcie_tx_tbl,
3258 .pcs = sdx55_qmp_pcie_pcs_tbl,
3296 .tx = sm8350_qmp_gen3x1_pcie_tx_tbl,
3300 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
3331 .tx = sm8350_qmp_gen3x2_pcie_tx_tbl,
3335 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
3344 .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl,
3366 .tx = sdx65_qmp_pcie_tx_tbl,
3370 .pcs = sdx65_qmp_pcie_pcs_tbl,
3393 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl,
3397 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
3428 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl,
3432 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl,
3473 .tx = sm8550_qmp_gen3x2_pcie_tx_tbl,
3477 .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl,
3500 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl,
3504 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl,
3533 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl,
3537 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl,
3565 .tx = sa8775p_qmp_gen4_pcie_tx_tbl,
3569 .pcs = sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl,
3587 .pcs = sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl,
3608 .tx = sa8775p_qmp_gen4_pcie_tx_tbl,
3612 .pcs = sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl,
3650 .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl,
3654 .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl,
3681 .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl,
3685 .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl,
3709 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_init_port_b()
3710 const struct qmp_pcie_offsets *offs = cfg->offsets; in qmp_pcie_init_port_b()
3711 void __iomem *serdes, *tx3, *rx3, *tx4, *rx4, *pcs, *pcs_misc, *ln_shrd; in qmp_pcie_init_port_b() local
3713 serdes = qmp->port_b + offs->serdes; in qmp_pcie_init_port_b()
3714 tx3 = qmp->port_b + offs->tx; in qmp_pcie_init_port_b()
3715 rx3 = qmp->port_b + offs->rx; in qmp_pcie_init_port_b()
3716 tx4 = qmp->port_b + offs->tx2; in qmp_pcie_init_port_b()
3717 rx4 = qmp->port_b + offs->rx2; in qmp_pcie_init_port_b()
3718 pcs = qmp->port_b + offs->pcs; in qmp_pcie_init_port_b()
3719 pcs_misc = qmp->port_b + offs->pcs_misc; in qmp_pcie_init_port_b()
3720 ln_shrd = qmp->port_b + offs->ln_shrd; in qmp_pcie_init_port_b()
3722 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); in qmp_pcie_init_port_b()
3723 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); in qmp_pcie_init_port_b()
3725 qmp_configure_lane(qmp->dev, tx3, tbls->tx, tbls->tx_num, 1); in qmp_pcie_init_port_b()
3726 qmp_configure_lane(qmp->dev, rx3, tbls->rx, tbls->rx_num, 1); in qmp_pcie_init_port_b()
3728 qmp_configure_lane(qmp->dev, tx4, tbls->tx, tbls->tx_num, 2); in qmp_pcie_init_port_b()
3729 qmp_configure_lane(qmp->dev, rx4, tbls->rx, tbls->rx_num, 2); in qmp_pcie_init_port_b()
3731 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); in qmp_pcie_init_port_b()
3732 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); in qmp_pcie_init_port_b()
3734 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); in qmp_pcie_init_port_b()
3739 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_init_registers()
3740 void __iomem *serdes = qmp->serdes; in qmp_pcie_init_registers()
3741 void __iomem *tx = qmp->tx; in qmp_pcie_init_registers() local
3742 void __iomem *rx = qmp->rx; in qmp_pcie_init_registers()
3743 void __iomem *tx2 = qmp->tx2; in qmp_pcie_init_registers()
3744 void __iomem *rx2 = qmp->rx2; in qmp_pcie_init_registers()
3745 void __iomem *pcs = qmp->pcs; in qmp_pcie_init_registers() local
3746 void __iomem *pcs_misc = qmp->pcs_misc; in qmp_pcie_init_registers()
3747 void __iomem *ln_shrd = qmp->ln_shrd; in qmp_pcie_init_registers()
3752 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); in qmp_pcie_init_registers()
3754 qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1); in qmp_pcie_init_registers()
3755 qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1); in qmp_pcie_init_registers()
3757 if (cfg->lanes >= 2) { in qmp_pcie_init_registers()
3758 qmp_configure_lane(qmp->dev, tx2, tbls->tx, tbls->tx_num, 2); in qmp_pcie_init_registers()
3759 qmp_configure_lane(qmp->dev, rx2, tbls->rx, tbls->rx_num, 2); in qmp_pcie_init_registers()
3762 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); in qmp_pcie_init_registers()
3763 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); in qmp_pcie_init_registers()
3765 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { in qmp_pcie_init_registers()
3766 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, in qmp_pcie_init_registers()
3767 cfg->serdes_4ln_num); in qmp_pcie_init_registers()
3771 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); in qmp_pcie_init_registers()
3777 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_init()
3780 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); in qmp_pcie_init()
3782 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); in qmp_pcie_init()
3786 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
3788 dev_err(qmp->dev, "reset assert failed\n"); in qmp_pcie_init()
3792 ret = reset_control_assert(qmp->nocsr_reset); in qmp_pcie_init()
3794 dev_err(qmp->dev, "no-csr reset assert failed\n"); in qmp_pcie_init()
3800 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
3802 dev_err(qmp->dev, "reset deassert failed\n"); in qmp_pcie_init()
3806 ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); in qmp_pcie_init()
3813 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
3815 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_pcie_init()
3823 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_exit()
3825 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_exit()
3827 clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); in qmp_pcie_exit()
3829 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_pcie_exit()
3837 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_power_on()
3839 void __iomem *pcs = qmp->pcs; in qmp_pcie_power_on() local
3844 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_pcie_power_on()
3845 cfg->pwrdn_ctrl); in qmp_pcie_power_on()
3847 if (qmp->mode == PHY_MODE_PCIE_RC) in qmp_pcie_power_on()
3848 mode_tbls = cfg->tbls_rc; in qmp_pcie_power_on()
3850 mode_tbls = cfg->tbls_ep; in qmp_pcie_power_on()
3852 qmp_pcie_init_registers(qmp, &cfg->tbls); in qmp_pcie_power_on()
3855 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); in qmp_pcie_power_on()
3859 ret = reset_control_deassert(qmp->nocsr_reset); in qmp_pcie_power_on()
3861 dev_err(qmp->dev, "no-csr reset deassert failed\n"); in qmp_pcie_power_on()
3866 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_power_on()
3868 /* start SerDes and Phy-Coding-Sublayer */ in qmp_pcie_power_on()
3869 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); in qmp_pcie_power_on()
3871 if (!cfg->skip_start_delay) in qmp_pcie_power_on()
3874 status = pcs + cfg->regs[QPHY_PCS_STATUS]; in qmp_pcie_power_on()
3875 mask = cfg->phy_status; in qmp_pcie_power_on()
3879 dev_err(qmp->dev, "phy initialization timed-out\n"); in qmp_pcie_power_on()
3886 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); in qmp_pcie_power_on()
3894 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_power_off()
3896 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); in qmp_pcie_power_off()
3899 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_power_off()
3901 /* stop SerDes and Phy-Coding-Sublayer */ in qmp_pcie_power_off()
3902 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], in qmp_pcie_power_off()
3906 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_pcie_power_off()
3907 cfg->pwrdn_ctrl); in qmp_pcie_power_off()
3945 qmp->mode = submode; in qmp_pcie_set_mode()
3948 dev_err(&phy->dev, "Unsupported submode %d\n", submode); in qmp_pcie_set_mode()
3949 return -EINVAL; in qmp_pcie_set_mode()
3964 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_vreg_init()
3965 struct device *dev = qmp->dev; in qmp_pcie_vreg_init()
3966 int num = cfg->num_vregs; in qmp_pcie_vreg_init()
3969 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); in qmp_pcie_vreg_init()
3970 if (!qmp->vregs) in qmp_pcie_vreg_init()
3971 return -ENOMEM; in qmp_pcie_vreg_init()
3974 qmp->vregs[i].supply = cfg->vreg_list[i]; in qmp_pcie_vreg_init()
3976 return devm_regulator_bulk_get(dev, num, qmp->vregs); in qmp_pcie_vreg_init()
3981 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_reset_init()
3982 struct device *dev = qmp->dev; in qmp_pcie_reset_init()
3986 qmp->resets = devm_kcalloc(dev, cfg->num_resets, in qmp_pcie_reset_init()
3987 sizeof(*qmp->resets), GFP_KERNEL); in qmp_pcie_reset_init()
3988 if (!qmp->resets) in qmp_pcie_reset_init()
3989 return -ENOMEM; in qmp_pcie_reset_init()
3991 for (i = 0; i < cfg->num_resets; i++) in qmp_pcie_reset_init()
3992 qmp->resets[i].id = cfg->reset_list[i]; in qmp_pcie_reset_init()
3994 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); in qmp_pcie_reset_init()
3998 if (cfg->has_nocsr_reset) { in qmp_pcie_reset_init()
3999 qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr"); in qmp_pcie_reset_init()
4000 if (IS_ERR(qmp->nocsr_reset)) in qmp_pcie_reset_init()
4001 return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), in qmp_pcie_reset_init()
4002 "failed to get no-csr reset\n"); in qmp_pcie_reset_init()
4010 struct device *dev = qmp->dev; in qmp_pcie_clk_init()
4014 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); in qmp_pcie_clk_init()
4015 if (!qmp->clks) in qmp_pcie_clk_init()
4016 return -ENOMEM; in qmp_pcie_clk_init()
4019 qmp->clks[i].id = qmp_pciephy_clk_l[i]; in qmp_pcie_clk_init()
4021 return devm_clk_bulk_get_optional(dev, num, qmp->clks); in qmp_pcie_clk_init()
4039 * +---------------+
4040 * | PHY block |<<---------------------------------------+
4042 * | +-------+ | +-----+ |
4043 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
4044 * clk | +-------+ | +-----+
4045 * +---------------+
4049 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; in phy_pipe_clk_register()
4053 ret = of_property_read_string_index(np, "clock-output-names", 0, &init.name); in phy_pipe_clk_register()
4055 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); in phy_pipe_clk_register()
4062 * Controllers using QMP PHY-s use 125MHz pipe clock interface in phy_pipe_clk_register()
4065 if (qmp->cfg->pipe_clock_rate) in phy_pipe_clk_register()
4066 fixed->fixed_rate = qmp->cfg->pipe_clock_rate; in phy_pipe_clk_register()
4068 fixed->fixed_rate = 125000000; in phy_pipe_clk_register()
4070 fixed->hw.init = &init; in phy_pipe_clk_register()
4072 return devm_clk_hw_register(qmp->dev, &fixed->hw); in phy_pipe_clk_register()
4085 * +---------------+
4086 * | PHY block |<<---------------------------------------------+
4088 * | +-------+ | +-----+ |
4089 * I/P---^-->| PLL |---^--->phy_aux_clksrc--->| GCC |--->phy_aux_clk---+
4090 * clk | +-------+ | +-----+
4091 * +---------------+
4095 struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed; in phy_aux_clk_register()
4099 snprintf(name, sizeof(name), "%s::phy_aux_clk", dev_name(qmp->dev)); in phy_aux_clk_register()
4104 fixed->fixed_rate = qmp->cfg->aux_clock_rate; in phy_aux_clk_register()
4105 fixed->hw.init = &init; in phy_aux_clk_register()
4107 return devm_clk_hw_register(qmp->dev, &fixed->hw); in phy_aux_clk_register()
4115 if (!clkspec->args_count) in qmp_pcie_clk_hw_get()
4116 return &qmp->pipe_clk_fixed.hw; in qmp_pcie_clk_hw_get()
4118 switch (clkspec->args[0]) { in qmp_pcie_clk_hw_get()
4120 return &qmp->pipe_clk_fixed.hw; in qmp_pcie_clk_hw_get()
4122 return &qmp->aux_clk_fixed.hw; in qmp_pcie_clk_hw_get()
4125 return ERR_PTR(-EINVAL); in qmp_pcie_clk_hw_get()
4136 if (qmp->cfg->aux_clock_rate) { in qmp_pcie_register_clocks()
4145 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw); in qmp_pcie_register_clocks()
4154 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); in qmp_pcie_register_clocks()
4159 struct platform_device *pdev = to_platform_device(qmp->dev); in qmp_pcie_parse_dt_legacy()
4160 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_parse_dt_legacy()
4161 struct device *dev = qmp->dev; in qmp_pcie_parse_dt_legacy()
4164 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); in qmp_pcie_parse_dt_legacy()
4165 if (IS_ERR(qmp->serdes)) in qmp_pcie_parse_dt_legacy()
4166 return PTR_ERR(qmp->serdes); in qmp_pcie_parse_dt_legacy()
4170 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. in qmp_pcie_parse_dt_legacy()
4171 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 in qmp_pcie_parse_dt_legacy()
4172 * For single lane PHYs: pcs_misc (optional) -> 3. in qmp_pcie_parse_dt_legacy()
4174 qmp->tx = devm_of_iomap(dev, np, 0, NULL); in qmp_pcie_parse_dt_legacy()
4175 if (IS_ERR(qmp->tx)) in qmp_pcie_parse_dt_legacy()
4176 return PTR_ERR(qmp->tx); in qmp_pcie_parse_dt_legacy()
4178 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) in qmp_pcie_parse_dt_legacy()
4179 qmp->rx = qmp->tx; in qmp_pcie_parse_dt_legacy()
4181 qmp->rx = devm_of_iomap(dev, np, 1, NULL); in qmp_pcie_parse_dt_legacy()
4182 if (IS_ERR(qmp->rx)) in qmp_pcie_parse_dt_legacy()
4183 return PTR_ERR(qmp->rx); in qmp_pcie_parse_dt_legacy()
4185 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); in qmp_pcie_parse_dt_legacy()
4186 if (IS_ERR(qmp->pcs)) in qmp_pcie_parse_dt_legacy()
4187 return PTR_ERR(qmp->pcs); in qmp_pcie_parse_dt_legacy()
4189 if (cfg->lanes >= 2) { in qmp_pcie_parse_dt_legacy()
4190 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); in qmp_pcie_parse_dt_legacy()
4191 if (IS_ERR(qmp->tx2)) in qmp_pcie_parse_dt_legacy()
4192 return PTR_ERR(qmp->tx2); in qmp_pcie_parse_dt_legacy()
4194 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); in qmp_pcie_parse_dt_legacy()
4195 if (IS_ERR(qmp->rx2)) in qmp_pcie_parse_dt_legacy()
4196 return PTR_ERR(qmp->rx2); in qmp_pcie_parse_dt_legacy()
4198 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); in qmp_pcie_parse_dt_legacy()
4200 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); in qmp_pcie_parse_dt_legacy()
4203 if (IS_ERR(qmp->pcs_misc) && in qmp_pcie_parse_dt_legacy()
4204 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) in qmp_pcie_parse_dt_legacy()
4205 qmp->pcs_misc = qmp->pcs + 0x400; in qmp_pcie_parse_dt_legacy()
4207 if (IS_ERR(qmp->pcs_misc)) { in qmp_pcie_parse_dt_legacy()
4208 if (cfg->tbls.pcs_misc || in qmp_pcie_parse_dt_legacy()
4209 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) || in qmp_pcie_parse_dt_legacy()
4210 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) { in qmp_pcie_parse_dt_legacy()
4211 return PTR_ERR(qmp->pcs_misc); in qmp_pcie_parse_dt_legacy()
4221 qmp->num_pipe_clks = 1; in qmp_pcie_parse_dt_legacy()
4222 qmp->pipe_clks[0].id = "pipe"; in qmp_pcie_parse_dt_legacy()
4223 qmp->pipe_clks[0].clk = clk; in qmp_pcie_parse_dt_legacy()
4234 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node, in qmp_pcie_get_4ln_config()
4235 "qcom,4ln-config-sel", in qmp_pcie_get_4ln_config()
4239 if (ret == -ENOENT) in qmp_pcie_get_4ln_config()
4242 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret); in qmp_pcie_get_4ln_config()
4248 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret); in qmp_pcie_get_4ln_config()
4252 qmp->tcsr_4ln_config = ret; in qmp_pcie_get_4ln_config()
4254 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config); in qmp_pcie_get_4ln_config()
4261 struct platform_device *pdev = to_platform_device(qmp->dev); in qmp_pcie_parse_dt()
4262 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_parse_dt()
4263 const struct qmp_pcie_offsets *offs = cfg->offsets; in qmp_pcie_parse_dt()
4264 struct device *dev = qmp->dev; in qmp_pcie_parse_dt()
4269 return -EINVAL; in qmp_pcie_parse_dt()
4279 qmp->serdes = base + offs->serdes; in qmp_pcie_parse_dt()
4280 qmp->pcs = base + offs->pcs; in qmp_pcie_parse_dt()
4281 qmp->pcs_misc = base + offs->pcs_misc; in qmp_pcie_parse_dt()
4282 qmp->tx = base + offs->tx; in qmp_pcie_parse_dt()
4283 qmp->rx = base + offs->rx; in qmp_pcie_parse_dt()
4285 if (cfg->lanes >= 2) { in qmp_pcie_parse_dt()
4286 qmp->tx2 = base + offs->tx2; in qmp_pcie_parse_dt()
4287 qmp->rx2 = base + offs->rx2; in qmp_pcie_parse_dt()
4290 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { in qmp_pcie_parse_dt()
4291 qmp->port_b = devm_platform_ioremap_resource(pdev, 1); in qmp_pcie_parse_dt()
4292 if (IS_ERR(qmp->port_b)) in qmp_pcie_parse_dt()
4293 return PTR_ERR(qmp->port_b); in qmp_pcie_parse_dt()
4296 if (cfg->tbls.ln_shrd) in qmp_pcie_parse_dt()
4297 qmp->ln_shrd = base + offs->ln_shrd; in qmp_pcie_parse_dt()
4299 qmp->num_pipe_clks = 2; in qmp_pcie_parse_dt()
4300 qmp->pipe_clks[0].id = "pipe"; in qmp_pcie_parse_dt()
4301 qmp->pipe_clks[1].id = "pipediv2"; in qmp_pcie_parse_dt()
4303 ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks); in qmp_pcie_parse_dt()
4307 ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1); in qmp_pcie_parse_dt()
4316 struct device *dev = &pdev->dev; in qmp_pcie_probe()
4324 return -ENOMEM; in qmp_pcie_probe()
4326 qmp->dev = dev; in qmp_pcie_probe()
4328 qmp->cfg = of_device_get_match_data(dev); in qmp_pcie_probe()
4329 if (!qmp->cfg) in qmp_pcie_probe()
4330 return -EINVAL; in qmp_pcie_probe()
4332 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); in qmp_pcie_probe()
4333 WARN_ON_ONCE(!qmp->cfg->phy_status); in qmp_pcie_probe()
4348 np = of_get_next_available_child(dev->of_node, NULL); in qmp_pcie_probe()
4352 np = of_node_get(dev->of_node); in qmp_pcie_probe()
4362 qmp->mode = PHY_MODE_PCIE_RC; in qmp_pcie_probe()
4364 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); in qmp_pcie_probe()
4365 if (IS_ERR(qmp->phy)) { in qmp_pcie_probe()
4366 ret = PTR_ERR(qmp->phy); in qmp_pcie_probe()
4371 phy_set_drvdata(qmp->phy, qmp); in qmp_pcie_probe()
4386 .compatible = "qcom,ipq6018-qmp-pcie-phy",
4389 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
4392 .compatible = "qcom,ipq8074-qmp-pcie-phy",
4395 .compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy",
4398 .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy",
4401 .compatible = "qcom,msm8998-qmp-pcie-phy",
4404 .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy",
4407 .compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy",
4410 .compatible = "qcom,sc8180x-qmp-pcie-phy",
4413 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy",
4416 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy",
4419 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy",
4422 .compatible = "qcom,sdm845-qhp-pcie-phy",
4425 .compatible = "qcom,sdm845-qmp-pcie-phy",
4428 .compatible = "qcom,sdx55-qmp-pcie-phy",
4431 .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy",
4434 .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy",
4437 .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy",
4440 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
4443 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
4446 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
4449 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
4452 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
4455 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
4458 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
4461 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",
4464 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",
4467 .compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy",
4470 .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy",
4473 .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy",
4476 .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy",
4479 .compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy",
4489 .name = "qcom-qmp-pcie-phy",