203 	writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |  in qcom_edp_phy_init()
211 	writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL);  in qcom_edp_phy_init()
214 	writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |  in qcom_edp_phy_init()
229 	writel(0xfc, edp->edp + DP_PHY_MODE);  in qcom_edp_phy_init()
231 	writel(0x00, edp->edp + DP_PHY_AUX_CFG0);  in qcom_edp_phy_init()
232 	writel(0x13, edp->edp + DP_PHY_AUX_CFG1);  in qcom_edp_phy_init()
233 	writel(0x24, edp->edp + DP_PHY_AUX_CFG2);  in qcom_edp_phy_init()
234 	writel(0x00, edp->edp + DP_PHY_AUX_CFG3);  in qcom_edp_phy_init()
235 	writel(0x0a, edp->edp + DP_PHY_AUX_CFG4);  in qcom_edp_phy_init()
236 	writel(0x26, edp->edp + DP_PHY_AUX_CFG5);  in qcom_edp_phy_init()
237 	writel(0x0a, edp->edp + DP_PHY_AUX_CFG6);  in qcom_edp_phy_init()
238 	writel(0x03, edp->edp + DP_PHY_AUX_CFG7);  in qcom_edp_phy_init()
239 	writel(cfg8, edp->edp + DP_PHY_AUX_CFG8);  in qcom_edp_phy_init()
240 	writel(0x03, edp->edp + DP_PHY_AUX_CFG9);  in qcom_edp_phy_init()
242 	writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |  in qcom_edp_phy_init()
290 	writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);  in qcom_edp_set_voltages()
291 	writel(swing, edp->tx0 + TXn_TX_DRV_LVL);  in qcom_edp_set_voltages()
292 	writel(emph, edp->tx0 + TXn_TX_EMP_POST1_LVL);  in qcom_edp_set_voltages()
294 	writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG);  in qcom_edp_set_voltages()
295 	writel(swing, edp->tx1 + TXn_TX_DRV_LVL);  in qcom_edp_set_voltages()
296 	writel(emph, edp->tx1 + TXn_TX_EMP_POST1_LVL);  in qcom_edp_set_voltages()
356 	writel(vco_div, edp->edp + DP_PHY_VCO_DIV);  in qcom_edp_set_vco_div()
365 	writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |  in qcom_edp_phy_power_on_v4()
369 	writel(0xfc, edp->edp + DP_PHY_MODE);  in qcom_edp_phy_power_on_v4()
379 	writel(0x20, edp->pll + QSERDES_V4_COM_RESETSM_CNTRL);  in qcom_edp_phy_com_resetsm_cntrl_v4()
388 	writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);  in qcom_edp_com_bias_en_clkbuflr_v4()
417 	writel(0x01, edp->pll + QSERDES_V4_COM_SSC_EN_CENTER);  in qcom_edp_com_configure_ssc_v4()
418 	writel(0x00, edp->pll + QSERDES_V4_COM_SSC_ADJ_PER1);  in qcom_edp_com_configure_ssc_v4()
419 	writel(0x36, edp->pll + QSERDES_V4_COM_SSC_PER1);  in qcom_edp_com_configure_ssc_v4()
420 	writel(0x01, edp->pll + QSERDES_V4_COM_SSC_PER2);  in qcom_edp_com_configure_ssc_v4()
421 	writel(step1, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0);  in qcom_edp_com_configure_ssc_v4()
422 	writel(step2, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0);  in qcom_edp_com_configure_ssc_v4()
479 	writel(0x01, edp->pll + QSERDES_V4_COM_SVS_MODE_CLK_SEL);  in qcom_edp_com_configure_pll_v4()
480 	writel(0x0b, edp->pll + QSERDES_V4_COM_SYSCLK_EN_SEL);  in qcom_edp_com_configure_pll_v4()
481 	writel(0x02, edp->pll + QSERDES_V4_COM_SYS_CLK_CTRL);  in qcom_edp_com_configure_pll_v4()
482 	writel(0x0c, edp->pll + QSERDES_V4_COM_CLK_ENABLE1);  in qcom_edp_com_configure_pll_v4()
483 	writel(0x06, edp->pll + QSERDES_V4_COM_SYSCLK_BUF_ENABLE);  in qcom_edp_com_configure_pll_v4()
484 	writel(0x30, edp->pll + QSERDES_V4_COM_CLK_SELECT);  in qcom_edp_com_configure_pll_v4()
485 	writel(hsclk_sel, edp->pll + QSERDES_V4_COM_HSCLK_SEL);  in qcom_edp_com_configure_pll_v4()
486 	writel(0x0f, edp->pll + QSERDES_V4_COM_PLL_IVCO);  in qcom_edp_com_configure_pll_v4()
487 	writel(0x08, edp->pll + QSERDES_V4_COM_LOCK_CMP_EN);  in qcom_edp_com_configure_pll_v4()
488 	writel(0x36, edp->pll + QSERDES_V4_COM_PLL_CCTRL_MODE0);  in qcom_edp_com_configure_pll_v4()
489 	writel(0x16, edp->pll + QSERDES_V4_COM_PLL_RCTRL_MODE0);  in qcom_edp_com_configure_pll_v4()
490 	writel(0x06, edp->pll + QSERDES_V4_COM_CP_CTRL_MODE0);  in qcom_edp_com_configure_pll_v4()
491 	writel(dec_start_mode0, edp->pll + QSERDES_V4_COM_DEC_START_MODE0);  in qcom_edp_com_configure_pll_v4()
492 	writel(0x00, edp->pll + QSERDES_V4_COM_DIV_FRAC_START1_MODE0);  in qcom_edp_com_configure_pll_v4()
493 	writel(div_frac_start2_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START2_MODE0);  in qcom_edp_com_configure_pll_v4()
494 	writel(div_frac_start3_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START3_MODE0);  in qcom_edp_com_configure_pll_v4()
495 	writel(0x02, edp->pll + QSERDES_V4_COM_CMN_CONFIG);  in qcom_edp_com_configure_pll_v4()
496 	writel(0x3f, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0);  in qcom_edp_com_configure_pll_v4()
497 	writel(0x00, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0);  in qcom_edp_com_configure_pll_v4()
498 	writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_MAP);  in qcom_edp_com_configure_pll_v4()
499 	writel(lock_cmp1_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP1_MODE0);  in qcom_edp_com_configure_pll_v4()
500 	writel(lock_cmp2_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP2_MODE0);  in qcom_edp_com_configure_pll_v4()
502 	writel(0x0a, edp->pll + QSERDES_V4_COM_BG_TIMER);  in qcom_edp_com_configure_pll_v4()
503 	writel(0x14, edp->pll + QSERDES_V4_COM_CORECLK_DIV_MODE0);  in qcom_edp_com_configure_pll_v4()
504 	writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_CTRL);  in qcom_edp_com_configure_pll_v4()
505 	writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);  in qcom_edp_com_configure_pll_v4()
506 	writel(0x0f, edp->pll + QSERDES_V4_COM_CORE_CLK_EN);  in qcom_edp_com_configure_pll_v4()
507 	writel(0xa0, edp->pll + QSERDES_V4_COM_VCO_TUNE1_MODE0);  in qcom_edp_com_configure_pll_v4()
508 	writel(0x03, edp->pll + QSERDES_V4_COM_VCO_TUNE2_MODE0);  in qcom_edp_com_configure_pll_v4()
540 	writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |  in qcom_edp_phy_power_on_v6()
544 	writel(0xfc, edp->edp + DP_PHY_MODE);  in qcom_edp_phy_power_on_v6()
554 	writel(0x20, edp->pll + QSERDES_V6_COM_RESETSM_CNTRL);  in qcom_edp_phy_com_resetsm_cntrl_v6()
563 	writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN);  in qcom_edp_com_bias_en_clkbuflr_v6()
592 	writel(0x01, edp->pll + QSERDES_V6_COM_SSC_EN_CENTER);  in qcom_edp_com_configure_ssc_v6()
593 	writel(0x00, edp->pll + QSERDES_V6_COM_SSC_ADJ_PER1);  in qcom_edp_com_configure_ssc_v6()
594 	writel(0x36, edp->pll + QSERDES_V6_COM_SSC_PER1);  in qcom_edp_com_configure_ssc_v6()
595 	writel(0x01, edp->pll + QSERDES_V6_COM_SSC_PER2);  in qcom_edp_com_configure_ssc_v6()
596 	writel(step1, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0);  in qcom_edp_com_configure_ssc_v6()
597 	writel(step2, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0);  in qcom_edp_com_configure_ssc_v6()
664 	writel(0x01, edp->pll + QSERDES_V6_COM_SVS_MODE_CLK_SEL);  in qcom_edp_com_configure_pll_v6()
665 	writel(0x0b, edp->pll + QSERDES_V6_COM_SYSCLK_EN_SEL);  in qcom_edp_com_configure_pll_v6()
666 	writel(0x02, edp->pll + QSERDES_V6_COM_SYS_CLK_CTRL);  in qcom_edp_com_configure_pll_v6()
667 	writel(0x0c, edp->pll + QSERDES_V6_COM_CLK_ENABLE1);  in qcom_edp_com_configure_pll_v6()
668 	writel(0x06, edp->pll + QSERDES_V6_COM_SYSCLK_BUF_ENABLE);  in qcom_edp_com_configure_pll_v6()
669 	writel(0x30, edp->pll + QSERDES_V6_COM_CLK_SELECT);  in qcom_edp_com_configure_pll_v6()
670 	writel(hsclk_sel, edp->pll + QSERDES_V6_COM_HSCLK_SEL_1);  in qcom_edp_com_configure_pll_v6()
671 	writel(0x07, edp->pll + QSERDES_V6_COM_PLL_IVCO);  in qcom_edp_com_configure_pll_v6()
672 	writel(0x08, edp->pll + QSERDES_V6_COM_LOCK_CMP_EN);  in qcom_edp_com_configure_pll_v6()
673 	writel(0x36, edp->pll + QSERDES_V6_COM_PLL_CCTRL_MODE0);  in qcom_edp_com_configure_pll_v6()
674 	writel(0x16, edp->pll + QSERDES_V6_COM_PLL_RCTRL_MODE0);  in qcom_edp_com_configure_pll_v6()
675 	writel(0x06, edp->pll + QSERDES_V6_COM_CP_CTRL_MODE0);  in qcom_edp_com_configure_pll_v6()
676 	writel(dec_start_mode0, edp->pll + QSERDES_V6_COM_DEC_START_MODE0);  in qcom_edp_com_configure_pll_v6()
677 	writel(0x00, edp->pll + QSERDES_V6_COM_DIV_FRAC_START1_MODE0);  in qcom_edp_com_configure_pll_v6()
678 	writel(div_frac_start2_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START2_MODE0);  in qcom_edp_com_configure_pll_v6()
679 	writel(div_frac_start3_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START3_MODE0);  in qcom_edp_com_configure_pll_v6()
680 	writel(0x12, edp->pll + QSERDES_V6_COM_CMN_CONFIG_1);  in qcom_edp_com_configure_pll_v6()
681 	writel(0x3f, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0);  in qcom_edp_com_configure_pll_v6()
682 	writel(0x00, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0);  in qcom_edp_com_configure_pll_v6()
683 	writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_MAP);  in qcom_edp_com_configure_pll_v6()
684 	writel(lock_cmp1_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP1_MODE0);  in qcom_edp_com_configure_pll_v6()
685 	writel(lock_cmp2_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP2_MODE0);  in qcom_edp_com_configure_pll_v6()
687 	writel(0x0a, edp->pll + QSERDES_V6_COM_BG_TIMER);  in qcom_edp_com_configure_pll_v6()
688 	writel(0x14, edp->pll + QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0);  in qcom_edp_com_configure_pll_v6()
689 	writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_CTRL);  in qcom_edp_com_configure_pll_v6()
690 	writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN);  in qcom_edp_com_configure_pll_v6()
691 	writel(0x0f, edp->pll + QSERDES_V6_COM_CORE_CLK_EN);  in qcom_edp_com_configure_pll_v6()
692 	writel(0xa0, edp->pll + QSERDES_V6_COM_VCO_TUNE1_MODE0);  in qcom_edp_com_configure_pll_v6()
693 	writel(0x03, edp->pll + QSERDES_V6_COM_VCO_TUNE2_MODE0);  in qcom_edp_com_configure_pll_v6()
695 	writel(code1_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0);  in qcom_edp_com_configure_pll_v6()
696 	writel(code2_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0);  in qcom_edp_com_configure_pll_v6()
731 	writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);  in qcom_edp_phy_power_on()
732 	writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG);  in qcom_edp_phy_power_on()
733 	writel(0x00, edp->tx0 + TXn_LANE_MODE_1);  in qcom_edp_phy_power_on()
734 	writel(0x00, edp->tx1 + TXn_LANE_MODE_1);  in qcom_edp_phy_power_on()
747 	writel(0x05, edp->edp + DP_PHY_TX0_TX1_LANE_CTL);  in qcom_edp_phy_power_on()
748 	writel(0x05, edp->edp + DP_PHY_TX2_TX3_LANE_CTL);  in qcom_edp_phy_power_on()
751 	writel(0x03, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN);  in qcom_edp_phy_power_on()
752 	writel(0x0f, edp->tx0 + TXn_CLKBUF_ENABLE);  in qcom_edp_phy_power_on()
753 	writel(0x03, edp->tx0 + TXn_RESET_TSYNC_EN);  in qcom_edp_phy_power_on()
754 	writel(0x01, edp->tx0 + TXn_TRAN_DRVR_EMP_EN);  in qcom_edp_phy_power_on()
755 	writel(0x04, edp->tx0 + TXn_TX_BAND);  in qcom_edp_phy_power_on()
758 	writel(0x03, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN);  in qcom_edp_phy_power_on()
759 	writel(0x0f, edp->tx1 + TXn_CLKBUF_ENABLE);  in qcom_edp_phy_power_on()
760 	writel(0x03, edp->tx1 + TXn_RESET_TSYNC_EN);  in qcom_edp_phy_power_on()
761 	writel(0x01, edp->tx1 + TXn_TRAN_DRVR_EMP_EN);  in qcom_edp_phy_power_on()
762 	writel(0x04, edp->tx1 + TXn_TX_BAND);  in qcom_edp_phy_power_on()
768 	writel(0x01, edp->edp + DP_PHY_CFG);  in qcom_edp_phy_power_on()
769 	writel(0x05, edp->edp + DP_PHY_CFG);  in qcom_edp_phy_power_on()
770 	writel(0x01, edp->edp + DP_PHY_CFG);  in qcom_edp_phy_power_on()
771 	writel(0x09, edp->edp + DP_PHY_CFG);  in qcom_edp_phy_power_on()
777 	writel(0x19, edp->edp + DP_PHY_CFG);  in qcom_edp_phy_power_on()
778 	writel(0x1f, edp->tx0 + TXn_HIGHZ_DRVR_EN);  in qcom_edp_phy_power_on()
779 	writel(0x04, edp->tx0 + TXn_HIGHZ_DRVR_EN);  in qcom_edp_phy_power_on()
780 	writel(0x00, edp->tx0 + TXn_TX_POL_INV);  in qcom_edp_phy_power_on()
781 	writel(0x1f, edp->tx1 + TXn_HIGHZ_DRVR_EN);  in qcom_edp_phy_power_on()
782 	writel(0x04, edp->tx1 + TXn_HIGHZ_DRVR_EN);  in qcom_edp_phy_power_on()
783 	writel(0x00, edp->tx1 + TXn_TX_POL_INV);  in qcom_edp_phy_power_on()
784 	writel(0x10, edp->tx0 + TXn_TX_DRV_LVL_OFFSET);  in qcom_edp_phy_power_on()
785 	writel(0x10, edp->tx1 + TXn_TX_DRV_LVL_OFFSET);  in qcom_edp_phy_power_on()
786 	writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX0);  in qcom_edp_phy_power_on()
787 	writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX1);  in qcom_edp_phy_power_on()
788 	writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX0);  in qcom_edp_phy_power_on()
789 	writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX1);  in qcom_edp_phy_power_on()
791 	writel(0x10, edp->tx0 + TXn_TX_EMP_POST1_LVL);  in qcom_edp_phy_power_on()
792 	writel(0x10, edp->tx1 + TXn_TX_EMP_POST1_LVL);  in qcom_edp_phy_power_on()
793 	writel(0x1f, edp->tx0 + TXn_TX_DRV_LVL);  in qcom_edp_phy_power_on()
794 	writel(0x1f, edp->tx1 + TXn_TX_DRV_LVL);  in qcom_edp_phy_power_on()
816 	writel(drvr0_en, edp->tx0 + TXn_HIGHZ_DRVR_EN);  in qcom_edp_phy_power_on()
817 	writel(bias0_en, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN);  in qcom_edp_phy_power_on()
818 	writel(drvr1_en, edp->tx1 + TXn_HIGHZ_DRVR_EN);  in qcom_edp_phy_power_on()
819 	writel(bias1_en, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN);  in qcom_edp_phy_power_on()
820 	writel(cfg1, edp->edp + DP_PHY_CFG_1);  in qcom_edp_phy_power_on()
822 	writel(0x18, edp->edp + DP_PHY_CFG);  in qcom_edp_phy_power_on()
825 	writel(0x19, edp->edp + DP_PHY_CFG);  in qcom_edp_phy_power_on()
842 	writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL);  in qcom_edp_phy_power_off()