Lines Matching +full:tx1 +full:- +full:3
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
17 #include <linux/phy/phy-dp.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp-dp-phy.h"
26 #include "phy-qcom-qmp-qserdes-com-v4.h"
27 #include "phy-qcom-qmp-qserdes-com-v6.h"
105 void __iomem *tx1; member
195 ret = regulator_bulk_enable(ARRAY_SIZE(edp->supplies), edp->supplies); in qcom_edp_phy_init()
199 ret = clk_bulk_prepare_enable(ARRAY_SIZE(edp->clks), edp->clks); in qcom_edp_phy_init()
205 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
207 ret = edp->cfg->ver_ops->com_bias_en_clkbuflr(edp); in qcom_edp_phy_init()
211 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
217 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
220 * TODO: Re-work the conditions around setting the cfg8 value in qcom_edp_phy_init()
224 if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) in qcom_edp_phy_init()
229 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_init()
231 writel(0x00, edp->edp + DP_PHY_AUX_CFG0); in qcom_edp_phy_init()
232 writel(0x13, edp->edp + DP_PHY_AUX_CFG1); in qcom_edp_phy_init()
233 writel(0x24, edp->edp + DP_PHY_AUX_CFG2); in qcom_edp_phy_init()
234 writel(0x00, edp->edp + DP_PHY_AUX_CFG3); in qcom_edp_phy_init()
235 writel(0x0a, edp->edp + DP_PHY_AUX_CFG4); in qcom_edp_phy_init()
236 writel(0x26, edp->edp + DP_PHY_AUX_CFG5); in qcom_edp_phy_init()
237 writel(0x0a, edp->edp + DP_PHY_AUX_CFG6); in qcom_edp_phy_init()
238 writel(0x03, edp->edp + DP_PHY_AUX_CFG7); in qcom_edp_phy_init()
239 writel(cfg8, edp->edp + DP_PHY_AUX_CFG8); in qcom_edp_phy_init()
240 writel(0x03, edp->edp + DP_PHY_AUX_CFG9); in qcom_edp_phy_init()
244 PHY_AUX_REQ_ERR_MASK, edp->edp + DP_PHY_AUX_INTERRUPT_MASK); in qcom_edp_phy_init()
251 regulator_bulk_disable(ARRAY_SIZE(edp->supplies), edp->supplies); in qcom_edp_phy_init()
258 const struct qcom_edp_swing_pre_emph_cfg *cfg = edp->cfg->swing_pre_emph_cfg; in qcom_edp_set_voltages()
269 if (edp->is_edp) in qcom_edp_set_voltages()
272 for (i = 0; i < dp_opts->lanes; i++) { in qcom_edp_set_voltages()
273 v_level = max(v_level, dp_opts->voltage[i]); in qcom_edp_set_voltages()
274 p_level = max(p_level, dp_opts->pre[i]); in qcom_edp_set_voltages()
277 if (dp_opts->link_rate <= 2700) { in qcom_edp_set_voltages()
278 swing = (*cfg->swing_hbr_rbr)[v_level][p_level]; in qcom_edp_set_voltages()
279 emph = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; in qcom_edp_set_voltages()
281 swing = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; in qcom_edp_set_voltages()
282 emph = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; in qcom_edp_set_voltages()
286 return -EINVAL; in qcom_edp_set_voltages()
288 ldo_config = edp->is_edp ? 0x0 : 0x1; in qcom_edp_set_voltages()
290 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); in qcom_edp_set_voltages()
291 writel(swing, edp->tx0 + TXn_TX_DRV_LVL); in qcom_edp_set_voltages()
292 writel(emph, edp->tx0 + TXn_TX_EMP_POST1_LVL); in qcom_edp_set_voltages()
294 writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); in qcom_edp_set_voltages()
295 writel(swing, edp->tx1 + TXn_TX_DRV_LVL); in qcom_edp_set_voltages()
296 writel(emph, edp->tx1 + TXn_TX_EMP_POST1_LVL); in qcom_edp_set_voltages()
303 const struct phy_configure_opts_dp *dp_opts = &opts->dp; in qcom_edp_phy_configure()
307 memcpy(&edp->dp_opts, dp_opts, sizeof(*dp_opts)); in qcom_edp_phy_configure()
309 if (dp_opts->set_voltages) in qcom_edp_phy_configure()
317 return edp->cfg->ver_ops->com_configure_ssc(edp); in qcom_edp_configure_ssc()
322 return edp->cfg->ver_ops->com_configure_pll(edp); in qcom_edp_configure_pll()
327 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_set_vco_div()
330 switch (dp_opts->link_rate) { in qcom_edp_set_vco_div()
353 return -EINVAL; in qcom_edp_set_vco_div()
356 writel(vco_div, edp->edp + DP_PHY_VCO_DIV); in qcom_edp_set_vco_div()
368 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_power_on_v4()
369 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_power_on_v4()
371 return readl_poll_timeout(edp->pll + QSERDES_V4_COM_CMN_STATUS, in qcom_edp_phy_power_on_v4()
379 writel(0x20, edp->pll + QSERDES_V4_COM_RESETSM_CNTRL); in qcom_edp_phy_com_resetsm_cntrl_v4()
381 return readl_poll_timeout(edp->pll + QSERDES_V4_COM_C_READY_STATUS, in qcom_edp_phy_com_resetsm_cntrl_v4()
388 writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); in qcom_edp_com_bias_en_clkbuflr_v4()
395 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_com_configure_ssc_v4()
399 switch (dp_opts->link_rate) { in qcom_edp_com_configure_ssc_v4()
414 return -EINVAL; in qcom_edp_com_configure_ssc_v4()
417 writel(0x01, edp->pll + QSERDES_V4_COM_SSC_EN_CENTER); in qcom_edp_com_configure_ssc_v4()
418 writel(0x00, edp->pll + QSERDES_V4_COM_SSC_ADJ_PER1); in qcom_edp_com_configure_ssc_v4()
419 writel(0x36, edp->pll + QSERDES_V4_COM_SSC_PER1); in qcom_edp_com_configure_ssc_v4()
420 writel(0x01, edp->pll + QSERDES_V4_COM_SSC_PER2); in qcom_edp_com_configure_ssc_v4()
421 writel(step1, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0); in qcom_edp_com_configure_ssc_v4()
422 writel(step2, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0); in qcom_edp_com_configure_ssc_v4()
429 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_com_configure_pll_v4()
437 switch (dp_opts->link_rate) { in qcom_edp_com_configure_pll_v4()
476 return -EINVAL; in qcom_edp_com_configure_pll_v4()
479 writel(0x01, edp->pll + QSERDES_V4_COM_SVS_MODE_CLK_SEL); in qcom_edp_com_configure_pll_v4()
480 writel(0x0b, edp->pll + QSERDES_V4_COM_SYSCLK_EN_SEL); in qcom_edp_com_configure_pll_v4()
481 writel(0x02, edp->pll + QSERDES_V4_COM_SYS_CLK_CTRL); in qcom_edp_com_configure_pll_v4()
482 writel(0x0c, edp->pll + QSERDES_V4_COM_CLK_ENABLE1); in qcom_edp_com_configure_pll_v4()
483 writel(0x06, edp->pll + QSERDES_V4_COM_SYSCLK_BUF_ENABLE); in qcom_edp_com_configure_pll_v4()
484 writel(0x30, edp->pll + QSERDES_V4_COM_CLK_SELECT); in qcom_edp_com_configure_pll_v4()
485 writel(hsclk_sel, edp->pll + QSERDES_V4_COM_HSCLK_SEL); in qcom_edp_com_configure_pll_v4()
486 writel(0x0f, edp->pll + QSERDES_V4_COM_PLL_IVCO); in qcom_edp_com_configure_pll_v4()
487 writel(0x08, edp->pll + QSERDES_V4_COM_LOCK_CMP_EN); in qcom_edp_com_configure_pll_v4()
488 writel(0x36, edp->pll + QSERDES_V4_COM_PLL_CCTRL_MODE0); in qcom_edp_com_configure_pll_v4()
489 writel(0x16, edp->pll + QSERDES_V4_COM_PLL_RCTRL_MODE0); in qcom_edp_com_configure_pll_v4()
490 writel(0x06, edp->pll + QSERDES_V4_COM_CP_CTRL_MODE0); in qcom_edp_com_configure_pll_v4()
491 writel(dec_start_mode0, edp->pll + QSERDES_V4_COM_DEC_START_MODE0); in qcom_edp_com_configure_pll_v4()
492 writel(0x00, edp->pll + QSERDES_V4_COM_DIV_FRAC_START1_MODE0); in qcom_edp_com_configure_pll_v4()
493 writel(div_frac_start2_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START2_MODE0); in qcom_edp_com_configure_pll_v4()
494 writel(div_frac_start3_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START3_MODE0); in qcom_edp_com_configure_pll_v4()
495 writel(0x02, edp->pll + QSERDES_V4_COM_CMN_CONFIG); in qcom_edp_com_configure_pll_v4()
496 writel(0x3f, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0); in qcom_edp_com_configure_pll_v4()
497 writel(0x00, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0); in qcom_edp_com_configure_pll_v4()
498 writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_MAP); in qcom_edp_com_configure_pll_v4()
499 writel(lock_cmp1_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP1_MODE0); in qcom_edp_com_configure_pll_v4()
500 writel(lock_cmp2_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP2_MODE0); in qcom_edp_com_configure_pll_v4()
502 writel(0x0a, edp->pll + QSERDES_V4_COM_BG_TIMER); in qcom_edp_com_configure_pll_v4()
503 writel(0x14, edp->pll + QSERDES_V4_COM_CORECLK_DIV_MODE0); in qcom_edp_com_configure_pll_v4()
504 writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_CTRL); in qcom_edp_com_configure_pll_v4()
505 writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); in qcom_edp_com_configure_pll_v4()
506 writel(0x0f, edp->pll + QSERDES_V4_COM_CORE_CLK_EN); in qcom_edp_com_configure_pll_v4()
507 writel(0xa0, edp->pll + QSERDES_V4_COM_VCO_TUNE1_MODE0); in qcom_edp_com_configure_pll_v4()
508 writel(0x03, edp->pll + QSERDES_V4_COM_VCO_TUNE2_MODE0); in qcom_edp_com_configure_pll_v4()
543 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_power_on_v6()
544 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_power_on_v6()
546 return readl_poll_timeout(edp->pll + QSERDES_V6_COM_CMN_STATUS, in qcom_edp_phy_power_on_v6()
554 writel(0x20, edp->pll + QSERDES_V6_COM_RESETSM_CNTRL); in qcom_edp_phy_com_resetsm_cntrl_v6()
556 return readl_poll_timeout(edp->pll + QSERDES_V6_COM_C_READY_STATUS, in qcom_edp_phy_com_resetsm_cntrl_v6()
563 writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN); in qcom_edp_com_bias_en_clkbuflr_v6()
570 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_com_configure_ssc_v6()
574 switch (dp_opts->link_rate) { in qcom_edp_com_configure_ssc_v6()
589 return -EINVAL; in qcom_edp_com_configure_ssc_v6()
592 writel(0x01, edp->pll + QSERDES_V6_COM_SSC_EN_CENTER); in qcom_edp_com_configure_ssc_v6()
593 writel(0x00, edp->pll + QSERDES_V6_COM_SSC_ADJ_PER1); in qcom_edp_com_configure_ssc_v6()
594 writel(0x36, edp->pll + QSERDES_V6_COM_SSC_PER1); in qcom_edp_com_configure_ssc_v6()
595 writel(0x01, edp->pll + QSERDES_V6_COM_SSC_PER2); in qcom_edp_com_configure_ssc_v6()
596 writel(step1, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0); in qcom_edp_com_configure_ssc_v6()
597 writel(step2, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0); in qcom_edp_com_configure_ssc_v6()
604 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_com_configure_pll_v6()
614 switch (dp_opts->link_rate) { in qcom_edp_com_configure_pll_v6()
661 return -EINVAL; in qcom_edp_com_configure_pll_v6()
664 writel(0x01, edp->pll + QSERDES_V6_COM_SVS_MODE_CLK_SEL); in qcom_edp_com_configure_pll_v6()
665 writel(0x0b, edp->pll + QSERDES_V6_COM_SYSCLK_EN_SEL); in qcom_edp_com_configure_pll_v6()
666 writel(0x02, edp->pll + QSERDES_V6_COM_SYS_CLK_CTRL); in qcom_edp_com_configure_pll_v6()
667 writel(0x0c, edp->pll + QSERDES_V6_COM_CLK_ENABLE1); in qcom_edp_com_configure_pll_v6()
668 writel(0x06, edp->pll + QSERDES_V6_COM_SYSCLK_BUF_ENABLE); in qcom_edp_com_configure_pll_v6()
669 writel(0x30, edp->pll + QSERDES_V6_COM_CLK_SELECT); in qcom_edp_com_configure_pll_v6()
670 writel(hsclk_sel, edp->pll + QSERDES_V6_COM_HSCLK_SEL_1); in qcom_edp_com_configure_pll_v6()
671 writel(0x07, edp->pll + QSERDES_V6_COM_PLL_IVCO); in qcom_edp_com_configure_pll_v6()
672 writel(0x08, edp->pll + QSERDES_V6_COM_LOCK_CMP_EN); in qcom_edp_com_configure_pll_v6()
673 writel(0x36, edp->pll + QSERDES_V6_COM_PLL_CCTRL_MODE0); in qcom_edp_com_configure_pll_v6()
674 writel(0x16, edp->pll + QSERDES_V6_COM_PLL_RCTRL_MODE0); in qcom_edp_com_configure_pll_v6()
675 writel(0x06, edp->pll + QSERDES_V6_COM_CP_CTRL_MODE0); in qcom_edp_com_configure_pll_v6()
676 writel(dec_start_mode0, edp->pll + QSERDES_V6_COM_DEC_START_MODE0); in qcom_edp_com_configure_pll_v6()
677 writel(0x00, edp->pll + QSERDES_V6_COM_DIV_FRAC_START1_MODE0); in qcom_edp_com_configure_pll_v6()
678 writel(div_frac_start2_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START2_MODE0); in qcom_edp_com_configure_pll_v6()
679 writel(div_frac_start3_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START3_MODE0); in qcom_edp_com_configure_pll_v6()
680 writel(0x12, edp->pll + QSERDES_V6_COM_CMN_CONFIG_1); in qcom_edp_com_configure_pll_v6()
681 writel(0x3f, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0); in qcom_edp_com_configure_pll_v6()
682 writel(0x00, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0); in qcom_edp_com_configure_pll_v6()
683 writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_MAP); in qcom_edp_com_configure_pll_v6()
684 writel(lock_cmp1_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP1_MODE0); in qcom_edp_com_configure_pll_v6()
685 writel(lock_cmp2_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP2_MODE0); in qcom_edp_com_configure_pll_v6()
687 writel(0x0a, edp->pll + QSERDES_V6_COM_BG_TIMER); in qcom_edp_com_configure_pll_v6()
688 writel(0x14, edp->pll + QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0); in qcom_edp_com_configure_pll_v6()
689 writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_CTRL); in qcom_edp_com_configure_pll_v6()
690 writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN); in qcom_edp_com_configure_pll_v6()
691 writel(0x0f, edp->pll + QSERDES_V6_COM_CORE_CLK_EN); in qcom_edp_com_configure_pll_v6()
692 writel(0xa0, edp->pll + QSERDES_V6_COM_VCO_TUNE1_MODE0); in qcom_edp_com_configure_pll_v6()
693 writel(0x03, edp->pll + QSERDES_V6_COM_VCO_TUNE2_MODE0); in qcom_edp_com_configure_pll_v6()
695 writel(code1_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0); in qcom_edp_com_configure_pll_v6()
696 writel(code2_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0); in qcom_edp_com_configure_pll_v6()
724 ret = edp->cfg->ver_ops->com_power_on(edp); in qcom_edp_phy_power_on()
728 if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) in qcom_edp_phy_power_on()
731 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); in qcom_edp_phy_power_on()
732 writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); in qcom_edp_phy_power_on()
733 writel(0x00, edp->tx0 + TXn_LANE_MODE_1); in qcom_edp_phy_power_on()
734 writel(0x00, edp->tx1 + TXn_LANE_MODE_1); in qcom_edp_phy_power_on()
736 if (edp->dp_opts.ssc) { in qcom_edp_phy_power_on()
747 writel(0x05, edp->edp + DP_PHY_TX0_TX1_LANE_CTL); in qcom_edp_phy_power_on()
748 writel(0x05, edp->edp + DP_PHY_TX2_TX3_LANE_CTL); in qcom_edp_phy_power_on()
750 /* TX-0 register configuration */ in qcom_edp_phy_power_on()
751 writel(0x03, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
752 writel(0x0f, edp->tx0 + TXn_CLKBUF_ENABLE); in qcom_edp_phy_power_on()
753 writel(0x03, edp->tx0 + TXn_RESET_TSYNC_EN); in qcom_edp_phy_power_on()
754 writel(0x01, edp->tx0 + TXn_TRAN_DRVR_EMP_EN); in qcom_edp_phy_power_on()
755 writel(0x04, edp->tx0 + TXn_TX_BAND); in qcom_edp_phy_power_on()
757 /* TX-1 register configuration */ in qcom_edp_phy_power_on()
758 writel(0x03, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
759 writel(0x0f, edp->tx1 + TXn_CLKBUF_ENABLE); in qcom_edp_phy_power_on()
760 writel(0x03, edp->tx1 + TXn_RESET_TSYNC_EN); in qcom_edp_phy_power_on()
761 writel(0x01, edp->tx1 + TXn_TRAN_DRVR_EMP_EN); in qcom_edp_phy_power_on()
762 writel(0x04, edp->tx1 + TXn_TX_BAND); in qcom_edp_phy_power_on()
768 writel(0x01, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
769 writel(0x05, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
770 writel(0x01, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
771 writel(0x09, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
773 ret = edp->cfg->ver_ops->com_resetsm_cntrl(edp); in qcom_edp_phy_power_on()
777 writel(0x19, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
778 writel(0x1f, edp->tx0 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
779 writel(0x04, edp->tx0 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
780 writel(0x00, edp->tx0 + TXn_TX_POL_INV); in qcom_edp_phy_power_on()
781 writel(0x1f, edp->tx1 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
782 writel(0x04, edp->tx1 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
783 writel(0x00, edp->tx1 + TXn_TX_POL_INV); in qcom_edp_phy_power_on()
784 writel(0x10, edp->tx0 + TXn_TX_DRV_LVL_OFFSET); in qcom_edp_phy_power_on()
785 writel(0x10, edp->tx1 + TXn_TX_DRV_LVL_OFFSET); in qcom_edp_phy_power_on()
786 writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX0); in qcom_edp_phy_power_on()
787 writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX1); in qcom_edp_phy_power_on()
788 writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX0); in qcom_edp_phy_power_on()
789 writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX1); in qcom_edp_phy_power_on()
791 writel(0x10, edp->tx0 + TXn_TX_EMP_POST1_LVL); in qcom_edp_phy_power_on()
792 writel(0x10, edp->tx1 + TXn_TX_EMP_POST1_LVL); in qcom_edp_phy_power_on()
793 writel(0x1f, edp->tx0 + TXn_TX_DRV_LVL); in qcom_edp_phy_power_on()
794 writel(0x1f, edp->tx1 + TXn_TX_DRV_LVL); in qcom_edp_phy_power_on()
796 if (edp->dp_opts.lanes == 1) { in qcom_edp_phy_power_on()
802 } else if (edp->dp_opts.lanes == 2) { in qcom_edp_phy_power_on()
816 writel(drvr0_en, edp->tx0 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
817 writel(bias0_en, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
818 writel(drvr1_en, edp->tx1 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
819 writel(bias1_en, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
820 writel(cfg1, edp->edp + DP_PHY_CFG_1); in qcom_edp_phy_power_on()
822 writel(0x18, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
825 writel(0x19, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
827 ret = readl_poll_timeout(edp->edp + DP_PHY_STATUS, in qcom_edp_phy_power_on()
832 clk_set_rate(edp->dp_link_hw.clk, edp->dp_opts.link_rate * 100000); in qcom_edp_phy_power_on()
833 clk_set_rate(edp->dp_pixel_hw.clk, pixel_freq); in qcom_edp_phy_power_on()
842 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_power_off()
852 return -EINVAL; in qcom_edp_phy_set_mode()
854 edp->is_edp = submode == PHY_SUBMODE_EDP; in qcom_edp_phy_set_mode()
863 clk_bulk_disable_unprepare(ARRAY_SIZE(edp->clks), edp->clks); in qcom_edp_phy_exit()
864 regulator_bulk_disable(ARRAY_SIZE(edp->supplies), edp->supplies); in qcom_edp_phy_exit()
882 * +------------------------------+
885 * | +-------------------+ |
887 * | +---------+---------+ |
889 * | +----------+-----------+ |
891 * | +----------+-----------+ |
892 * +------------------------------+
894 * +---------<---------v------------>----------+
896 * +--------v----------------+ |
899 * +--------+----------------+ |
908 * +--------<------------+-----------------+---<---+
910 * +----v---------+ +--------v-----+ +--------v------+
915 * +-------+------+ +-----+--------+ +--------+------+
917 * v---->----------v-------------<------v
919 * +----------+-----------------+
921 * +---------+------------------+
931 switch (req->rate) { in qcom_edp_dp_pixel_clk_determine_rate()
938 return -EINVAL; in qcom_edp_dp_pixel_clk_determine_rate()
946 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_dp_pixel_clk_recalc_rate()
948 switch (dp_opts->link_rate) { in qcom_edp_dp_pixel_clk_recalc_rate()
970 switch (req->rate) { in qcom_edp_dp_link_clk_determine_rate()
978 return -EINVAL; in qcom_edp_dp_link_clk_determine_rate()
986 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_dp_link_clk_recalc_rate()
988 switch (dp_opts->link_rate) { in qcom_edp_dp_link_clk_recalc_rate()
993 return dp_opts->link_rate * 100000; in qcom_edp_dp_link_clk_recalc_rate()
1012 data = devm_kzalloc(edp->dev, struct_size(data, hws, 2), GFP_KERNEL); in qcom_edp_clks_register()
1014 return -ENOMEM; in qcom_edp_clks_register()
1015 data->num = 2; in qcom_edp_clks_register()
1017 snprintf(name, sizeof(name), "%s::link_clk", dev_name(edp->dev)); in qcom_edp_clks_register()
1020 edp->dp_link_hw.init = &init; in qcom_edp_clks_register()
1021 ret = devm_clk_hw_register(edp->dev, &edp->dp_link_hw); in qcom_edp_clks_register()
1025 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(edp->dev)); in qcom_edp_clks_register()
1028 edp->dp_pixel_hw.init = &init; in qcom_edp_clks_register()
1029 ret = devm_clk_hw_register(edp->dev, &edp->dp_pixel_hw); in qcom_edp_clks_register()
1033 data->hws[0] = &edp->dp_link_hw; in qcom_edp_clks_register()
1034 data->hws[1] = &edp->dp_pixel_hw; in qcom_edp_clks_register()
1036 return devm_of_clk_add_hw_provider(edp->dev, of_clk_hw_onecell_get, data); in qcom_edp_clks_register()
1042 struct device *dev = &pdev->dev; in qcom_edp_phy_probe()
1048 return -ENOMEM; in qcom_edp_phy_probe()
1050 edp->dev = dev; in qcom_edp_phy_probe()
1051 edp->cfg = of_device_get_match_data(&pdev->dev); in qcom_edp_phy_probe()
1052 edp->is_edp = edp->cfg->is_edp; in qcom_edp_phy_probe()
1054 edp->edp = devm_platform_ioremap_resource(pdev, 0); in qcom_edp_phy_probe()
1055 if (IS_ERR(edp->edp)) in qcom_edp_phy_probe()
1056 return PTR_ERR(edp->edp); in qcom_edp_phy_probe()
1058 edp->tx0 = devm_platform_ioremap_resource(pdev, 1); in qcom_edp_phy_probe()
1059 if (IS_ERR(edp->tx0)) in qcom_edp_phy_probe()
1060 return PTR_ERR(edp->tx0); in qcom_edp_phy_probe()
1062 edp->tx1 = devm_platform_ioremap_resource(pdev, 2); in qcom_edp_phy_probe()
1063 if (IS_ERR(edp->tx1)) in qcom_edp_phy_probe()
1064 return PTR_ERR(edp->tx1); in qcom_edp_phy_probe()
1066 edp->pll = devm_platform_ioremap_resource(pdev, 3); in qcom_edp_phy_probe()
1067 if (IS_ERR(edp->pll)) in qcom_edp_phy_probe()
1068 return PTR_ERR(edp->pll); in qcom_edp_phy_probe()
1070 edp->clks[0].id = "aux"; in qcom_edp_phy_probe()
1071 edp->clks[1].id = "cfg_ahb"; in qcom_edp_phy_probe()
1072 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(edp->clks), edp->clks); in qcom_edp_phy_probe()
1076 edp->supplies[0].supply = "vdda-phy"; in qcom_edp_phy_probe()
1077 edp->supplies[1].supply = "vdda-pll"; in qcom_edp_phy_probe()
1078 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(edp->supplies), edp->supplies); in qcom_edp_phy_probe()
1082 ret = regulator_set_load(edp->supplies[0].consumer, 21800); /* 1.2 V vdda-phy */ in qcom_edp_phy_probe()
1084 dev_err(dev, "failed to set load at %s\n", edp->supplies[0].supply); in qcom_edp_phy_probe()
1088 ret = regulator_set_load(edp->supplies[1].consumer, 36000); /* 0.9 V vdda-pll */ in qcom_edp_phy_probe()
1090 dev_err(dev, "failed to set load at %s\n", edp->supplies[1].supply); in qcom_edp_phy_probe()
1094 ret = qcom_edp_clks_register(edp, pdev->dev.of_node); in qcom_edp_phy_probe()
1098 edp->phy = devm_phy_create(dev, pdev->dev.of_node, &qcom_edp_ops); in qcom_edp_phy_probe()
1099 if (IS_ERR(edp->phy)) { in qcom_edp_phy_probe()
1101 return PTR_ERR(edp->phy); in qcom_edp_phy_probe()
1104 phy_set_drvdata(edp->phy, edp); in qcom_edp_phy_probe()
1111 { .compatible = "qcom,sc7280-edp-phy", .data = &sc7280_dp_phy_cfg, },
1112 { .compatible = "qcom,sc8180x-edp-phy", .data = &sc7280_dp_phy_cfg, },
1113 { .compatible = "qcom,sc8280xp-dp-phy", .data = &sc8280xp_dp_phy_cfg, },
1114 { .compatible = "qcom,sc8280xp-edp-phy", .data = &sc8280xp_edp_phy_cfg, },
1115 { .compatible = "qcom,x1e80100-dp-phy", .data = &x1e80100_phy_cfg, },
1123 .name = "qcom-edp-phy",