104 	void __iomem *tx0;  member
290 	writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);  in qcom_edp_set_voltages()
291 	writel(swing, edp->tx0 + TXn_TX_DRV_LVL);  in qcom_edp_set_voltages()
292 	writel(emph, edp->tx0 + TXn_TX_EMP_POST1_LVL);  in qcom_edp_set_voltages()
731 	writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);  in qcom_edp_phy_power_on()
733 	writel(0x00, edp->tx0 + TXn_LANE_MODE_1);  in qcom_edp_phy_power_on()
751 	writel(0x03, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN);  in qcom_edp_phy_power_on()
752 	writel(0x0f, edp->tx0 + TXn_CLKBUF_ENABLE);  in qcom_edp_phy_power_on()
753 	writel(0x03, edp->tx0 + TXn_RESET_TSYNC_EN);  in qcom_edp_phy_power_on()
754 	writel(0x01, edp->tx0 + TXn_TRAN_DRVR_EMP_EN);  in qcom_edp_phy_power_on()
755 	writel(0x04, edp->tx0 + TXn_TX_BAND);  in qcom_edp_phy_power_on()
778 	writel(0x1f, edp->tx0 + TXn_HIGHZ_DRVR_EN);  in qcom_edp_phy_power_on()
779 	writel(0x04, edp->tx0 + TXn_HIGHZ_DRVR_EN);  in qcom_edp_phy_power_on()
780 	writel(0x00, edp->tx0 + TXn_TX_POL_INV);  in qcom_edp_phy_power_on()
784 	writel(0x10, edp->tx0 + TXn_TX_DRV_LVL_OFFSET);  in qcom_edp_phy_power_on()
786 	writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX0);  in qcom_edp_phy_power_on()
787 	writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX1);  in qcom_edp_phy_power_on()
791 	writel(0x10, edp->tx0 + TXn_TX_EMP_POST1_LVL);  in qcom_edp_phy_power_on()
793 	writel(0x1f, edp->tx0 + TXn_TX_DRV_LVL);  in qcom_edp_phy_power_on()
816 	writel(drvr0_en, edp->tx0 + TXn_HIGHZ_DRVR_EN);  in qcom_edp_phy_power_on()
817 	writel(bias0_en, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN);  in qcom_edp_phy_power_on()
1058 	edp->tx0 = devm_platform_ioremap_resource(pdev, 1);  in qcom_edp_phy_probe()
1059 	if (IS_ERR(edp->tx0))  in qcom_edp_phy_probe()
1060 		return PTR_ERR(edp->tx0);  in qcom_edp_phy_probe()